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-rw-r--r--test/MC/ARM/neon-absdiff-encoding.ll2
-rw-r--r--test/MC/ARM/neon-add-encoding.ll2
-rw-r--r--test/MC/ARM/neon-bitwise-encoding.ll2
-rw-r--r--test/MC/ARM/neon-cmp-encoding.ll2
-rw-r--r--test/MC/ARM/neon-minmax-encoding.ll2
-rw-r--r--test/MC/ARM/neon-mul-accum-encoding.ll2
-rw-r--r--test/MC/ARM/neon-mul-encoding.ll2
-rw-r--r--test/MC/ARM/neon-pairwise-encoding.ll2
-rw-r--r--test/MC/ARM/neon-reciprocal-encoding.ll2
-rw-r--r--test/MC/ARM/neon-satshift-encoding.ll2
-rw-r--r--test/MC/ARM/neon-shift-encoding.ll2
-rw-r--r--test/MC/ARM/neon-shiftaccum-encoding.ll2
-rw-r--r--test/MC/ARM/neon-shuffle-encoding.ll2
-rw-r--r--test/MC/ARM/neon-sub-encoding.ll2
-rw-r--r--test/MC/ARM/neon-table-encoding.ll1
-rw-r--r--test/MC/ARM/simple-fp-encoding.ll1
16 files changed, 30 insertions, 0 deletions
diff --git a/test/MC/ARM/neon-absdiff-encoding.ll b/test/MC/ARM/neon-absdiff-encoding.ll
index f0adf39..8c649f1 100644
--- a/test/MC/ARM/neon-absdiff-encoding.ll
+++ b/test/MC/ARM/neon-absdiff-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/MC/ARM/neon-add-encoding.ll b/test/MC/ARM/neon-add-encoding.ll
index 1bffba0..62290fb 100644
--- a/test/MC/ARM/neon-add-encoding.ll
+++ b/test/MC/ARM/neon-add-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
; CHECK: vadd_8xi8
define <8 x i8> @vadd_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
diff --git a/test/MC/ARM/neon-bitwise-encoding.ll b/test/MC/ARM/neon-bitwise-encoding.ll
index 3a3ba92..ebfff60 100644
--- a/test/MC/ARM/neon-bitwise-encoding.ll
+++ b/test/MC/ARM/neon-bitwise-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
; FIXME: The following instructions still require testing:
; - vand with immediate, vorr with immediate
; - both vbit and vbif
diff --git a/test/MC/ARM/neon-cmp-encoding.ll b/test/MC/ARM/neon-cmp-encoding.ll
index c12bef0..2600a98 100644
--- a/test/MC/ARM/neon-cmp-encoding.ll
+++ b/test/MC/ARM/neon-cmp-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
; FIXME: We cannot currently test the following instructions, which are
; currently marked as for-disassembly only in the .td files:
; - VCEQz
diff --git a/test/MC/ARM/neon-minmax-encoding.ll b/test/MC/ARM/neon-minmax-encoding.ll
index 913519e..6108ab6 100644
--- a/test/MC/ARM/neon-minmax-encoding.ll
+++ b/test/MC/ARM/neon-minmax-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/MC/ARM/neon-mul-accum-encoding.ll b/test/MC/ARM/neon-mul-accum-encoding.ll
index 3543a42..20f93cc 100644
--- a/test/MC/ARM/neon-mul-accum-encoding.ll
+++ b/test/MC/ARM/neon-mul-accum-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
; CHECK: vmla_8xi8
define <8 x i8> @vmla_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
%tmp1 = load <8 x i8>* %A
diff --git a/test/MC/ARM/neon-mul-encoding.ll b/test/MC/ARM/neon-mul-encoding.ll
index 907ff18..79513a1 100644
--- a/test/MC/ARM/neon-mul-encoding.ll
+++ b/test/MC/ARM/neon-mul-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
; CHECK: vmul_8xi8
define <8 x i8> @vmul_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
diff --git a/test/MC/ARM/neon-pairwise-encoding.ll b/test/MC/ARM/neon-pairwise-encoding.ll
index d8ef192..f7fea53 100644
--- a/test/MC/ARM/neon-pairwise-encoding.ll
+++ b/test/MC/ARM/neon-pairwise-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/MC/ARM/neon-reciprocal-encoding.ll b/test/MC/ARM/neon-reciprocal-encoding.ll
index cab5e93..85fd65f 100644
--- a/test/MC/ARM/neon-reciprocal-encoding.ll
+++ b/test/MC/ARM/neon-reciprocal-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
diff --git a/test/MC/ARM/neon-satshift-encoding.ll b/test/MC/ARM/neon-satshift-encoding.ll
index 4cf6b1d..0f0bee2 100644
--- a/test/MC/ARM/neon-satshift-encoding.ll
+++ b/test/MC/ARM/neon-satshift-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
diff --git a/test/MC/ARM/neon-shift-encoding.ll b/test/MC/ARM/neon-shift-encoding.ll
index bc8aeee..8a4780e 100644
--- a/test/MC/ARM/neon-shift-encoding.ll
+++ b/test/MC/ARM/neon-shift-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
; CHECK: vshls_8xi8
define <8 x i8> @vshls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
diff --git a/test/MC/ARM/neon-shiftaccum-encoding.ll b/test/MC/ARM/neon-shiftaccum-encoding.ll
index e2e7109..ab6630c 100644
--- a/test/MC/ARM/neon-shiftaccum-encoding.ll
+++ b/test/MC/ARM/neon-shiftaccum-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
diff --git a/test/MC/ARM/neon-shuffle-encoding.ll b/test/MC/ARM/neon-shuffle-encoding.ll
index 273a528..98ccf42 100644
--- a/test/MC/ARM/neon-shuffle-encoding.ll
+++ b/test/MC/ARM/neon-shuffle-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
diff --git a/test/MC/ARM/neon-sub-encoding.ll b/test/MC/ARM/neon-sub-encoding.ll
index 94a2639..5ebbc63 100644
--- a/test/MC/ARM/neon-sub-encoding.ll
+++ b/test/MC/ARM/neon-sub-encoding.ll
@@ -1,5 +1,7 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
+
; CHECK: vsub_8xi8
define <8 x i8> @vsub_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
diff --git a/test/MC/ARM/neon-table-encoding.ll b/test/MC/ARM/neon-table-encoding.ll
index 1352855..285b097 100644
--- a/test/MC/ARM/neon-table-encoding.ll
+++ b/test/MC/ARM/neon-table-encoding.ll
@@ -1,5 +1,6 @@
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+; XFAIL: *
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
index b941069..f807757 100644
--- a/test/MC/ARM/simple-fp-encoding.ll
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -1,5 +1,6 @@
; RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
+; XFAIL: *
; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
; should run on .s source files rather than using llc to generate the
generated by cgit v1.1 at 2025-08-15 22:29:42 +0000