diff options
Diffstat (limited to 'test')
132 files changed, 3265 insertions, 142 deletions
diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index 7aae3ac..a8afc20 100644 --- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s +; RUN: llc -mcpu=cortex-a8 -mattr=-neonfp < %s | FileCheck %s ; PR5423 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/test/CodeGen/ARM/2010-12-07-PEIBug.ll index 23e1aa1..770ad44 100644 --- a/test/CodeGen/ARM/2010-12-07-PEIBug.ll +++ b/test/CodeGen/ARM/2010-12-07-PEIBug.ll @@ -4,36 +4,12 @@ define hidden void @foo() nounwind ssp { entry: ; CHECK: foo: -; CHECK: push {r7, lr} -; CHECK-NEXT: mov r7, sp +; CHECK: mov r7, sp ; CHECK-NEXT: vpush {d8} ; CHECK-NEXT: vpush {d10, d11} - %tmp40 = load <4 x i8>* undef - %tmp41 = extractelement <4 x i8> %tmp40, i32 2 - %conv42 = zext i8 %tmp41 to i32 - %conv43 = sitofp i32 %conv42 to float - %div44 = fdiv float %conv43, 2.560000e+02 - %vecinit45 = insertelement <4 x float> undef, float %div44, i32 2 - %vecinit46 = insertelement <4 x float> %vecinit45, float 1.000000e+00, i32 3 - store <4 x float> %vecinit46, <4 x float>* undef - br i1 undef, label %if.then105, label %if.else109 - -if.then105: ; preds = %entry - br label %if.end114 - -if.else109: ; preds = %entry - br label %if.end114 - -if.end114: ; preds = %if.else109, %if.then105 - %call185 = call float @bar() - %vecinit186 = insertelement <4 x float> undef, float %call185, i32 1 - %call189 = call float @bar() - %vecinit190 = insertelement <4 x float> %vecinit186, float %call189, i32 2 - %vecinit191 = insertelement <4 x float> %vecinit190, float 1.000000e+00, i32 3 - store <4 x float> %vecinit191, <4 x float>* undef + tail call void asm sideeffect "","~{d8},~{d10},~{d11}"() nounwind ; CHECK: vpop {d10, d11} ; CHECK-NEXT: vpop {d8} -; CHECK-NEXT: pop {r7, pc} ret void } diff --git a/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll b/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll new file mode 100644 index 0000000..c9ea691 --- /dev/null +++ b/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=arm -mcpu=cortex-a8 -verify-machineinstrs < %s +; PR12165 +target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-p:32:32:32-v128:32:32" +target triple = "arm-none-linux" + +define hidden void @_strtod_r() nounwind { + br i1 undef, label %1, label %2 + +; <label>:1 ; preds = %0 + br label %2 + +; <label>:2 ; preds = %1, %0 + br i1 undef, label %3, label %8 + +; <label>:3 ; preds = %2 + br i1 undef, label %4, label %7 + +; <label>:4 ; preds = %3 + %5 = call i32 @llvm.flt.rounds() + %6 = icmp eq i32 %5, 1 + br i1 %6, label %8, label %7 + +; <label>:7 ; preds = %4, %3 + unreachable + +; <label>:8 ; preds = %4, %2 + br i1 undef, label %9, label %10 + +; <label>:9 ; preds = %8 + br label %10 + +; <label>:10 ; preds = %9, %8 + ret void +} + +declare i32 @llvm.flt.rounds() nounwind diff --git a/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll b/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll new file mode 100644 index 0000000..6d596df --- /dev/null +++ b/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s +; rdar://11035895 + +; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to +; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e. +; (i32 extload $addr+c*sizeof(i16) +define void @test_hi_short3(<3 x i16> * nocapture %srcA, <2 x i16> * nocapture %dst) nounwind { +entry: +; CHECK: ldrh [[REG:r[0-9]+]] +; CHECK: strh [[REG]] + %0 = load <3 x i16> * %srcA, align 8 + %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef> + store <2 x i16> %1, <2 x i16> * %dst, align 4 + ret void +} + diff --git a/test/CodeGen/ARM/fast-isel-cmp-imm.ll b/test/CodeGen/ARM/fast-isel-cmp-imm.ll index 1693066..660156a 100644 --- a/test/CodeGen/ARM/fast-isel-cmp-imm.ll +++ b/test/CodeGen/ARM/fast-isel-cmp-imm.ll @@ -229,3 +229,22 @@ if.then: ; preds = %entry if.end: ; preds = %if.then, %entry ret void } + +; rdar://11038907 +; When comparing LONG_MIN/INT_MIN use a cmp instruction. +define void @t13() nounwind ssp { +entry: +; ARM: t13 +; THUMB: t13 + %cmp = icmp slt i32 -123, -2147483648 +; ARM: cmp r{{[0-9]}}, #-2147483648 +; THUMB: cmp.w r{{[0-9]}}, #-2147483648 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + ret void + +if.end: ; preds = %entry + ret void +} + diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll index 80925c7..2d8f710 100644 --- a/test/CodeGen/ARM/fpcmp-opt.ll +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -9,7 +9,7 @@ entry: ; CHECK: vldr [[S0:s[0-9]+]], ; CHECK: vldr [[S1:s[0-9]+]], ; CHECK: vcmpe.f32 [[S1]], [[S0]] -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: beq %0 = load float* %a %1 = load float* %b diff --git a/test/CodeGen/ARM/fpcmp_ueq.ll b/test/CodeGen/ARM/fpcmp_ueq.ll index 2e6b3e3..4a4c5b1 100644 --- a/test/CodeGen/ARM/fpcmp_ueq.ll +++ b/test/CodeGen/ARM/fpcmp_ueq.ll @@ -5,7 +5,7 @@ define i32 @f7(float %a, float %b) { entry: ; CHECK: f7: ; CHECK: vcmpe.f32 -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: movweq ; CHECK-NOT: vmrs ; CHECK: movwvs diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll index 63f8557..0f142ee 100644 --- a/test/CodeGen/ARM/ifcvt11.ll +++ b/test/CodeGen/ARM/ifcvt11.ll @@ -18,7 +18,7 @@ bb.nph: ; preds = %entry bb: ; preds = %bb4, %bb.nph ; CHECK: vcmpe.f64 -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr %r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ] %n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ] %scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0 @@ -33,7 +33,7 @@ bb1: ; preds = %bb ; CHECK-NOT: vcmpemi ; CHECK-NOT: vmrsmi ; CHECK: vcmpe.f64 -; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: vmrs APSR_nzcv, fpscr %scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2 %6 = load double* %scevgep12, align 4 %7 = fcmp uge double %3, %6 diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll index 3cb8a8e..c50a233 100644 --- a/test/CodeGen/ARM/mul_const.ll +++ b/test/CodeGen/ARM/mul_const.ll @@ -41,3 +41,45 @@ entry: ret i32 %0 } +define i32 @tn9(i32 %v) nounwind readnone { +entry: +; CHECK: tn9: +; CHECK: add r0, r0, r0, lsl #3 +; CHECK: rsb r0, r0, #0 + %0 = mul i32 %v, -9 + ret i32 %0 +} + +define i32 @tn7(i32 %v) nounwind readnone { +entry: +; CHECK: tn7: +; CHECK: sub r0, r0, r0, lsl #3 + %0 = mul i32 %v, -7 + ret i32 %0 +} + +define i32 @tn5(i32 %v) nounwind readnone { +entry: +; CHECK: tn5: +; CHECK: add r0, r0, r0, lsl #2 +; CHECK: rsb r0, r0, #0 + %0 = mul i32 %v, -5 + ret i32 %0 +} + +define i32 @tn3(i32 %v) nounwind readnone { +entry: +; CHECK: tn3: +; CHECK: sub r0, r0, r0, lsl #2 + %0 = mul i32 %v, -3 + ret i32 %0 +} + +define i32 @tn12288(i32 %v) nounwind readnone { +entry: +; CHECK: tn12288: +; CHECK: sub r0, r0, r0, lsl #2 +; CHECK: lsl{{.*}}#12 + %0 = mul i32 %v, -12288 + ret i32 %0 +} diff --git a/test/CodeGen/ARM/neon_spill.ll b/test/CodeGen/ARM/neon_spill.ll index 677b9c2..277bd05 100644 --- a/test/CodeGen/ARM/neon_spill.ll +++ b/test/CodeGen/ARM/neon_spill.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -verify-machineinstrs +; RUN: llc < %s -verify-machineinstrs -O0 ; PR12177 ; ; This test case spills a QQQQ register. diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index 3a66ec5..ca2e18a 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -67,7 +67,7 @@ entry: ; T2: t5: ; T2-NOT: moveq -; T2: orreq.w r2, r2, #1 +; T2: orreq r2, r2, #1 %tmp1 = icmp eq i32 %a, %b %tmp2 = zext i1 %tmp1 to i32 %tmp3 = or i32 %tmp2, %c diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 521ffa1..eb971ff 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -54,12 +54,16 @@ declare i8* @malloc(...) define fastcc void @test4(i16 %addr) nounwind { entry: ; A8: test4: -; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A8: str [[REG]], [r0] +; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A8: str [[REG]], [r0, r1, lsl #2] +; A8-NOT: str [[REG]], [r0] ; A9: test4: -; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A9: str [[REG]], [r0] +; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A9: str [[REG]], [r0, r1, lsl #2] +; A9-NOT: str [[REG]], [r0] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 diff --git a/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll index f518843..9c4838a 100644 --- a/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll +++ b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll @@ -1,7 +1,6 @@ -; RUN: llc < %s +; RUN: llc -march=mips -soft-float < %s ; PR2667 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "psp" %struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] } %struct.__FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*, i8*, i32)*, i32 (i8*, i8*, i32)*, i32 (i8*, i32, i32)*, i32 (i8*)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i32, %struct._reent*, i32 } %struct.__sbuf = type { i8*, i32 } diff --git a/test/CodeGen/Mips/zeroreg.ll b/test/CodeGen/Mips/zeroreg.ll new file mode 100644 index 0000000..b890e1d --- /dev/null +++ b/test/CodeGen/Mips/zeroreg.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s + +@g1 = external global i32 + +define i32 @foo0(i32 %s) nounwind readonly { +entry: +; CHECK-NOT: addiu +; CHECK: movn + %tobool = icmp ne i32 %s, 0 + %0 = load i32* @g1, align 4, !tbaa !0 + %cond = select i1 %tobool, i32 0, i32 %0 + ret i32 %cond +} + +define i32 @foo1(i32 %s) nounwind readonly { +entry: +; CHECK-NOT: addiu +; CHECK: movz + %tobool = icmp ne i32 %s, 0 + %0 = load i32* @g1, align 4, !tbaa !0 + %cond = select i1 %tobool, i32 %0, i32 0 + ret i32 %cond +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/X86/2012-03-15-build_vector_wl.ll b/test/CodeGen/X86/2012-03-15-build_vector_wl.ll new file mode 100644 index 0000000..fec17e9 --- /dev/null +++ b/test/CodeGen/X86/2012-03-15-build_vector_wl.ll @@ -0,0 +1,10 @@ + +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; CHECK: build_vector_again +define <4 x i8> @build_vector_again(<16 x i8> %in) nounwind readnone { +entry: + %out = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK: shufb + ret <4 x i8> %out +; CHECK: ret +} diff --git a/test/CodeGen/X86/2012-03-20-LargeConstantExpr.ll b/test/CodeGen/X86/2012-03-20-LargeConstantExpr.ll new file mode 100644 index 0000000..d24647e --- /dev/null +++ b/test/CodeGen/X86/2012-03-20-LargeConstantExpr.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; <rdar://problem/11070338> +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; CHECK: _.memset_pattern: +; CHECK-NEXT: .quad 4575657222473777152 +; CHECK-NEXT: .quad 4575657222473777152 + +@.memset_pattern = internal unnamed_addr constant i128 or (i128 zext (i64 bitcast (<2 x float> <float 1.000000e+00, float 1.000000e+00> to i64) to i128), i128 shl (i128 zext (i64 bitcast (<2 x float> <float 1.000000e+00, float 1.000000e+00> to i64) to i128), i128 64)), align 16 + +define void @foo(i8* %a, i64 %b) { + call void @memset_pattern16(i8* %a, i8* bitcast (i128* @.memset_pattern to i8*), i64 %b) + ret void +} + +declare void @memset_pattern16(i8*, i8*, i64) diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll index 947d79f..54f01e9 100644 --- a/test/CodeGen/X86/avx-shuffle.ll +++ b/test/CodeGen/X86/avx-shuffle.ll @@ -135,3 +135,15 @@ define <4 x i32> @test15(<2 x i32>%x) nounwind readnone { ret <4 x i32>%x1 } +; rdar://10974078 +define <8 x float> @test16(float* nocapture %f) nounwind uwtable readonly ssp { +entry: + %0 = bitcast float* %f to <4 x float>* + %1 = load <4 x float>* %0, align 8 +; CHECK: test16 +; CHECK: vmovups +; CHECK-NOT: vxorps +; CHECK-NOT: vinsertf128 + %shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4> + ret <8 x float> %shuffle.i +} diff --git a/test/CodeGen/X86/avx-vextractf128.ll b/test/CodeGen/X86/avx-vextractf128.ll index dccf901b..fe0f6ca 100644 --- a/test/CodeGen/X86/avx-vextractf128.ll +++ b/test/CodeGen/X86/avx-vextractf128.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; CHECK: @A ; CHECK-NOT: vunpck ; CHECK: vextractf128 $1 define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp { @@ -8,6 +9,7 @@ entry: ret <8 x float> %shuffle } +; CHECK: @B ; CHECK-NOT: vunpck ; CHECK: vextractf128 $1 define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp { @@ -16,3 +18,89 @@ entry: ret <4 x double> %shuffle } +; CHECK: @t0 +; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0 +; CHECK-NOT: vmovaps %xmm0, (%rdi) +; CHECK: vextractf128 $0, %ymm0, (%rdi) +define void @t0(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp { +entry: + %0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0) + %1 = bitcast float* %addr to <4 x float>* + store <4 x float> %0, <4 x float>* %1, align 16 + ret void +} + +declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone + +; CHECK: @t1 +; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0 +; CHECK-NOT: vmovups %xmm0, (%rdi) +; CHECK: vextractf128 $0, %ymm0, (%rdi) +define void @t1(float* %addr, <8 x float> %a) nounwind uwtable ssp { +entry: + %0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0) + %1 = bitcast float* %addr to i8* + tail call void @llvm.x86.sse.storeu.ps(i8* %1, <4 x float> %0) + ret void +} + +declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind + +; CHECK: @t2 +; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0 +; CHECK-NOT: vmovaps %xmm0, (%rdi) +; CHECK: vextractf128 $0, %ymm0, (%rdi) +define void @t2(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp { +entry: + %0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0) + %1 = bitcast double* %addr to <2 x double>* + store <2 x double> %0, <2 x double>* %1, align 16 + ret void +} + +declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone + +; CHECK: @t3 +; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0 +; CHECK-NOT: vmovups %xmm0, (%rdi) +; CHECK: vextractf128 $0, %ymm0, (%rdi) +define void @t3(double* %addr, <4 x double> %a) nounwind uwtable ssp { +entry: + %0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0) + %1 = bitcast double* %addr to i8* + tail call void @llvm.x86.sse2.storeu.pd(i8* %1, <2 x double> %0) + ret void +} + +declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind + +; CHECK: @t4 +; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0 +; CHECK-NOT: vmovaps %xmm0, (%rdi) +; CHECK: vextractf128 $0, %ymm0, (%rdi) +define void @t4(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp { +entry: + %0 = bitcast <4 x i64> %a to <8 x i32> + %1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0) + %2 = bitcast <4 x i32> %1 to <2 x i64> + store <2 x i64> %2, <2 x i64>* %addr, align 16 + ret void +} + +declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone + +; CHECK: @t5 +; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0 +; CHECK-NOT: vmovdqu %xmm0, (%rdi) +; CHECK: vextractf128 $0, %ymm0, (%rdi) +define void @t5(<2 x i64>* %addr, <4 x i64> %a) nounwind uwtable ssp { +entry: + %0 = bitcast <4 x i64> %a to <8 x i32> + %1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0) + %2 = bitcast <2 x i64>* %addr to i8* + %3 = bitcast <4 x i32> %1 to <16 x i8> + tail call void @llvm.x86.sse2.storeu.dq(i8* %2, <16 x i8> %3) + ret void +} + +declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind diff --git a/test/CodeGen/X86/avx-vinsertf128.ll b/test/CodeGen/X86/avx-vinsertf128.ll index def2212..9a954fe 100644 --- a/test/CodeGen/X86/avx-vinsertf128.ll +++ b/test/CodeGen/X86/avx-vinsertf128.ll @@ -104,3 +104,28 @@ ret <8 x i32> %res } declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone +; rdar://10643481 +; CHECK: vinsertf128_combine +define <8 x float> @vinsertf128_combine(float* nocapture %f) nounwind uwtable readonly ssp { +; CHECK-NOT: vmovaps +; CHECK: vinsertf128 +entry: + %add.ptr = getelementptr inbounds float* %f, i64 4 + %0 = bitcast float* %add.ptr to <4 x float>* + %1 = load <4 x float>* %0, align 16 + %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1) + ret <8 x float> %2 +} + +; rdar://11076953 +; CHECK: vinsertf128_ucombine +define <8 x float> @vinsertf128_ucombine(float* nocapture %f) nounwind uwtable readonly ssp { +; CHECK-NOT: vmovups +; CHECK: vinsertf128 +entry: + %add.ptr = getelementptr inbounds float* %f, i64 4 + %0 = bitcast float* %add.ptr to <4 x float>* + %1 = load <4 x float>* %0, align 8 + %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1) + ret <8 x float> %2 +} diff --git a/test/CodeGen/X86/legalize-shift-64.ll b/test/CodeGen/X86/legalize-shift-64.ll index 2026472..c9f2fc2 100644 --- a/test/CodeGen/X86/legalize-shift-64.ll +++ b/test/CodeGen/X86/legalize-shift-64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 < %s | FileCheck %s +; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s define i64 @test1(i32 %xx, i32 %test) nounwind { %conv = zext i32 %xx to i64 diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index 527a5a6..1311a73 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -1,4 +1,5 @@ ; XFAIL: * +; ...should pass. See PR12324: misched bringup ; RUN: llc < %s -march=x86-64 -O3 -asm-verbose=false | FileCheck %s target datalayout = "e-p:64:64:64" target triple = "x86_64-unknown-unknown" diff --git a/test/CodeGen/X86/misched-new.ll b/test/CodeGen/X86/misched-new.ll new file mode 100644 index 0000000..f3c2af8 --- /dev/null +++ b/test/CodeGen/X86/misched-new.ll @@ -0,0 +1,25 @@ +; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup < %s +; XFAIL: * +; ...should pass. See PR12324: misched bringup +; +; Interesting MachineScheduler cases. + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +; From oggenc. +; After coalescing, we have a dead superreg (RAX) definition. +; +; CHECK: xorl %esi, %esi +; CHECK: movl $32, %ecx +; CHECK: rep;movsl +define fastcc void @_preextrapolate_helper() nounwind uwtable ssp { +entry: + br i1 undef, label %for.cond.preheader, label %if.end + +for.cond.preheader: ; preds = %entry + call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 128, i32 4, i1 false) nounwind + unreachable + +if.end: ; preds = %entry + ret void +} diff --git a/test/CodeGen/X86/remat-scalar-zero.ll b/test/CodeGen/X86/remat-scalar-zero.ll index f6f0ed1..75f438d 100644 --- a/test/CodeGen/X86/remat-scalar-zero.ll +++ b/test/CodeGen/X86/remat-scalar-zero.ll @@ -1,4 +1,5 @@ ; XFAIL: * +; ...should pass. See PR12324: misched bringup ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu > %t ; RUN: not grep xor %t ; RUN: not grep movap %t diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll index cea9e9c..6432ae3 100644 --- a/test/CodeGen/X86/zext-sext.ll +++ b/test/CodeGen/X86/zext-sext.ll @@ -1,4 +1,5 @@ ; XFAIL: * +; ...should pass. See PR12324: misched bringup ; RUN: llc < %s -march=x86-64 | FileCheck %s ; <rdar://problem/8006248> diff --git a/test/DebugInfo/X86/DW_AT_specification.ll b/test/DebugInfo/X86/DW_AT_specification.ll index e4c5c80..078b740 100644 --- a/test/DebugInfo/X86/DW_AT_specification.ll +++ b/test/DebugInfo/X86/DW_AT_specification.ll @@ -3,8 +3,8 @@ ; test that the DW_AT_specification is a back edge in the file. -; CHECK: 0x00000038: DW_TAG_subprogram [5] * -; CHECK: 0x0000005e: DW_AT_specification [DW_FORM_ref4] (cu + 0x0038 => {0x00000038}) +; CHECK: 0x0000003a: DW_TAG_subprogram [5] * +; CHECK: 0x00000060: DW_AT_specification [DW_FORM_ref4] (cu + 0x003a => {0x0000003a}) @_ZZN3foo3barEvE1x = constant i32 0, align 4 diff --git a/test/DebugInfo/X86/concrete_out_of_line.ll b/test/DebugInfo/X86/concrete_out_of_line.ll index 055a9bf..a227071 100644 --- a/test/DebugInfo/X86/concrete_out_of_line.ll +++ b/test/DebugInfo/X86/concrete_out_of_line.ll @@ -7,7 +7,7 @@ ; first check that we have a TAG_subprogram at a given offset and it has ; AT_inline. -; CHECK: 0x00000130: DW_TAG_subprogram [18] +; CHECK: 0x00000134: DW_TAG_subprogram [18] ; CHECK-NEXT: DW_AT_MIPS_linkage_name ; CHECK-NEXT: DW_AT_specification ; CHECK-NEXT: DW_AT_inline @@ -15,8 +15,8 @@ ; and then that a TAG_subprogram refers to it with AT_abstract_origin. -; CHECK: 0x00000180: DW_TAG_subprogram [20] -; CHECK-NEXT: DW_AT_abstract_origin [DW_FORM_ref4] (cu + 0x0130 => {0x00000130}) +; CHECK: 0x00000184: DW_TAG_subprogram [20] +; CHECK-NEXT: DW_AT_abstract_origin [DW_FORM_ref4] (cu + 0x0134 => {0x00000134}) define i32 @_ZN17nsAutoRefCnt7ReleaseEv() { entry: diff --git a/test/DebugInfo/X86/objc-fwd-decl.ll b/test/DebugInfo/X86/objc-fwd-decl.ll new file mode 100644 index 0000000..1a815f9 --- /dev/null +++ b/test/DebugInfo/X86/objc-fwd-decl.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple=x86_64-macosx %s -o %t -filetype=obj +; RUN: llvm-dwarfdump %t | FileCheck %s + +; CHECK: 0x00000027: DW_TAG_structure_type +; CHECK: 0x0000002c: DW_AT_declaration +; CHECK: 0x0000002d: DW_AT_APPLE_runtime_class + +%0 = type opaque + +@a = common global %0* null, align 8 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!9, !10, !11, !12} + +!0 = metadata !{i32 786449, i32 0, i32 16, metadata !"foo.m", metadata !"/Users/echristo", metadata !"clang version 3.1 (trunk 152054 trunk 152094)", i1 true, i1 false, metadata !"", i32 2, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ] +!1 = metadata !{metadata !2} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{metadata !5} +!5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 3, metadata !7, i32 0, i32 1, %0** @a} ; [ DW_TAG_variable ] +!6 = metadata !{i32 786473, metadata !"foo.m", metadata !"/Users/echristo", null} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] +!8 = metadata !{i32 786451, null, metadata !"FooBarBaz", metadata !6, i32 1, i32 0, i32 0, i32 0, i32 4, null, null, i32 16} ; [ DW_TAG_structure_type ] +!9 = metadata !{i32 1, metadata !"Objective-C Version", i32 2} +!10 = metadata !{i32 1, metadata !"Objective-C Image Info Version", i32 0} +!11 = metadata !{i32 1, metadata !"Objective-C Image Info Section", metadata !"__DATA, __objc_imageinfo, regular, no_dead_strip"} +!12 = metadata !{i32 4, metadata !"Objective-C Garbage Collection", i32 0} diff --git a/test/DebugInfo/X86/pr11300.ll b/test/DebugInfo/X86/pr11300.ll index 8488434..5a001ee 100644 --- a/test/DebugInfo/X86/pr11300.ll +++ b/test/DebugInfo/X86/pr11300.ll @@ -3,8 +3,8 @@ ; test that the DW_AT_specification is a back edge in the file. -; CHECK: 0x0000005a: DW_TAG_subprogram [5] -; CHECK: 0x0000007a: DW_AT_specification [DW_FORM_ref4] (cu + 0x005a => {0x0000005a}) +; CHECK: 0x0000005c: DW_TAG_subprogram [5] +; CHECK: 0x0000007c: DW_AT_specification [DW_FORM_ref4] (cu + 0x005c => {0x0000005c}) %struct.foo = type { i8 } diff --git a/test/DebugInfo/X86/struct-loc.ll b/test/DebugInfo/X86/struct-loc.ll new file mode 100644 index 0000000..9a04738 --- /dev/null +++ b/test/DebugInfo/X86/struct-loc.ll @@ -0,0 +1,26 @@ +; RUN: llc -mtriple=x86_64-apple-darwin %s -o %t -filetype=obj +; RUN: llvm-dwarfdump %t | FileCheck %s + +; Make sure that structures have a decl file and decl line attached. +; CHECK: DW_TAG_structure_type [3] +; CHECK: DW_AT_decl_file +; CHECK: DW_AT_decl_line +; CHECK: DW_TAG_member + +%struct.foo = type { i32 } + +@f = common global %struct.foo zeroinitializer, align 4 + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"struct_bug.c", metadata !"/Users/echristo/tmp", metadata !"clang version 3.1 (trunk 152837) (llvm/trunk 152845)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ] +!1 = metadata !{metadata !2} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{metadata !5} +!5 = metadata !{i32 786484, i32 0, null, metadata !"f", metadata !"f", metadata !"", metadata !6, i32 5, metadata !7, i32 0, i32 1, %struct.foo* @f} ; [ DW_TAG_variable ] +!6 = metadata !{i32 786473, metadata !"struct_bug.c", metadata !"/Users/echristo/tmp", null} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786451, null, metadata !"foo", metadata !6, i32 1, i64 32, i64 32, i32 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!8 = metadata !{metadata !9} +!9 = metadata !{i32 786445, metadata !7, metadata !"a", metadata !6, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/bug_null_debuginfo.ll b/test/DebugInfo/bug_null_debuginfo.ll new file mode 100644 index 0000000..a7fdf70 --- /dev/null +++ b/test/DebugInfo/bug_null_debuginfo.ll @@ -0,0 +1,6 @@ +; RUN: llc + + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{null, null, null} diff --git a/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll b/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll new file mode 100644 index 0000000..46273d3 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll @@ -0,0 +1,37 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +@.LC0 = internal global [10 x i8] c"argc: %d\0A\00" ; <[10 x i8]*> [#uses=1] + +declare i32 @puts(i8*) + +define void @getoptions(i32* %argc) { +bb0: + ret void +} + +declare i32 @printf(i8*, ...) + +define i32 @main(i32 %argc, i8** %argv) { +bb0: + call i32 (i8*, ...)* @printf( i8* getelementptr ([10 x i8]* @.LC0, i64 0, i64 0), i32 %argc ) ; <i32>:0 [#uses=0] + %cast224 = bitcast i8** %argv to i8* ; <i8*> [#uses=1] + %local = alloca i8* ; <i8**> [#uses=3] + store i8* %cast224, i8** %local + %cond226 = icmp sle i32 %argc, 0 ; <i1> [#uses=1] + br i1 %cond226, label %bb3, label %bb2 +bb2: ; preds = %bb2, %bb0 + %cann-indvar = phi i32 [ 0, %bb0 ], [ %add1-indvar, %bb2 ] ; <i32> [#uses=2] + %add1-indvar = add i32 %cann-indvar, 1 ; <i32> [#uses=2] + %cann-indvar-idxcast = sext i32 %cann-indvar to i64 ; <i64> [#uses=1] + %CT = bitcast i8** %local to i8*** ; <i8***> [#uses=1] + %reg115 = load i8*** %CT ; <i8**> [#uses=1] + %cast235 = getelementptr i8** %reg115, i64 %cann-indvar-idxcast ; <i8**> [#uses=1] + %reg117 = load i8** %cast235 ; <i8*> [#uses=1] + %reg236 = call i32 @puts( i8* %reg117 ) ; <i32> [#uses=0] + %cond239 = icmp slt i32 %add1-indvar, %argc ; <i1> [#uses=1] + br i1 %cond239, label %bb2, label %bb3 +bb3: ; preds = %bb2, %bb0 + %cast243 = bitcast i8** %local to i32* ; <i32*> [#uses=1] + call void @getoptions( i32* %cast243 ) + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll b/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll new file mode 100644 index 0000000..88bfbb3 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll @@ -0,0 +1,13 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @foo(i32 %X, i32 %Y, double %A) { + %cond212 = fcmp une double %A, 1.000000e+00 ; <i1> [#uses=1] + %cast110 = zext i1 %cond212 to i32 ; <i32> [#uses=1] + ret i32 %cast110 +} + +define i32 @main() { + %reg212 = call i32 @foo( i32 0, i32 1, double 1.000000e+00 ) ; <i32> [#uses=1] + ret i32 %reg212 +} + diff --git a/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll b/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll new file mode 100644 index 0000000..d5f860d --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll @@ -0,0 +1,20 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { + call i32 @mylog( i32 4 ) ; <i32>:1 [#uses=0] + ret i32 0 +} + +define internal i32 @mylog(i32 %num) { +bb0: + br label %bb2 +bb2: ; preds = %bb2, %bb0 + %reg112 = phi i32 [ 10, %bb2 ], [ 1, %bb0 ] ; <i32> [#uses=1] + %cann-indvar = phi i32 [ %cann-indvar, %bb2 ], [ 0, %bb0 ] ; <i32> [#uses=1] + %reg114 = add i32 %reg112, 1 ; <i32> [#uses=2] + %cond222 = icmp slt i32 %reg114, %num ; <i1> [#uses=1] + br i1 %cond222, label %bb2, label %bb3 +bb3: ; preds = %bb2 + ret i32 %reg114 +} + diff --git a/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll b/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll new file mode 100644 index 0000000..721f2e8 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll @@ -0,0 +1,12 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { +; <label>:0 + br label %Loop +Loop: ; preds = %Loop, %0 + %X = phi i32 [ 0, %0 ], [ 1, %Loop ] ; <i32> [#uses=1] + br i1 true, label %Out, label %Loop +Out: ; preds = %Loop + ret i32 %X +} + diff --git a/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll b/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll new file mode 100644 index 0000000..d17df99 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll @@ -0,0 +1,11 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; We were accidentally inverting the signedness of right shifts. Whoops. + +define i32 @main() { + %X = ashr i32 -1, 16 ; <i32> [#uses=1] + %Y = ashr i32 %X, 16 ; <i32> [#uses=1] + %Z = add i32 %Y, 1 ; <i32> [#uses=1] + ret i32 %Z +} + diff --git a/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll b/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll new file mode 100644 index 0000000..e55cb06 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll @@ -0,0 +1,10 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { + %X = fadd double 0.000000e+00, 1.000000e+00 ; <double> [#uses=1] + %Y = fsub double 0.000000e+00, 1.000000e+00 ; <double> [#uses=2] + %Z = fcmp oeq double %X, %Y ; <i1> [#uses=0] + fadd double %Y, 0.000000e+00 ; <double>:1 [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll b/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll new file mode 100644 index 0000000..663dc40 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll @@ -0,0 +1,17 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @bar(i8* %X) { + ; pointer should be 4 byte aligned! + %P = alloca double ; <double*> [#uses=1] + %R = ptrtoint double* %P to i32 ; <i32> [#uses=1] + %A = and i32 %R, 3 ; <i32> [#uses=1] + ret i32 %A +} + +define i32 @main() { + %SP = alloca i8 ; <i8*> [#uses=1] + %X = add i32 0, 0 ; <i32> [#uses=1] + alloca i8, i32 %X ; <i8*>:1 [#uses=0] + call i32 @bar( i8* %SP ) ; <i32>:2 [#uses=1] + ret i32 %2 +} diff --git a/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll b/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll new file mode 100644 index 0000000..e95294b --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll @@ -0,0 +1,19 @@ +; This testcase should return with an exit code of 1. +; +; RUN: not %lli -use-mcjit %s + +@test = global i64 0 ; <i64*> [#uses=1] + +define internal i64 @test.upgrd.1() { + %tmp.0 = load i64* @test ; <i64> [#uses=1] + %tmp.1 = add i64 %tmp.0, 1 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + +define i32 @main() { + %L = call i64 @test.upgrd.1( ) ; <i64> [#uses=1] + %I = trunc i64 %L to i32 ; <i32> [#uses=1] + ret i32 %I +} + + diff --git a/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll b/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll new file mode 100644 index 0000000..a237194 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll @@ -0,0 +1,11 @@ +; RUN: %lli -use-mcjit %s test + +declare i32 @puts(i8*) + +define i32 @main(i32 %argc.1, i8** %argv.1) { + %tmp.5 = getelementptr i8** %argv.1, i64 1 ; <i8**> [#uses=1] + %tmp.6 = load i8** %tmp.5 ; <i8*> [#uses=1] + %tmp.0 = call i32 @puts( i8* %tmp.6 ) ; <i32> [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll b/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll new file mode 100644 index 0000000..70464a3 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll @@ -0,0 +1,15 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +target datalayout = "e-p:32:32" + +define i32 @main() { +entry: + br label %endif +then: ; No predecessors! + br label %endif +endif: ; preds = %then, %entry + %x = phi i32 [ 4, %entry ], [ 27, %then ] ; <i32> [#uses=0] + %result = phi i32 [ 32, %then ], [ 0, %entry ] ; <i32> [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll b/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll new file mode 100644 index 0000000..58d423f --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll @@ -0,0 +1,19 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; Testcase distilled from 256.bzip2. + +target datalayout = "e-p:32:32" + +define i32 @main() { +entry: + br label %loopentry.0 +loopentry.0: ; preds = %loopentry.0, %entry + %h.0 = phi i32 [ %tmp.2, %loopentry.0 ], [ -1, %entry ] ; <i32> [#uses=1] + %tmp.2 = add i32 %h.0, 1 ; <i32> [#uses=3] + %tmp.4 = icmp ne i32 %tmp.2, 0 ; <i1> [#uses=1] + br i1 %tmp.4, label %loopentry.0, label %loopentry.1 +loopentry.1: ; preds = %loopentry.0 + %h.1 = phi i32 [ %tmp.2, %loopentry.0 ] ; <i32> [#uses=1] + ret i32 %h.1 +} + diff --git a/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll b/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll new file mode 100644 index 0000000..a22fe07 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll @@ -0,0 +1,17 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; Testcase distilled from 256.bzip2. + +target datalayout = "e-p:32:32" + +define i32 @main() { +entry: + %X = add i32 1, -1 ; <i32> [#uses=3] + br label %Next +Next: ; preds = %entry + %A = phi i32 [ %X, %entry ] ; <i32> [#uses=0] + %B = phi i32 [ %X, %entry ] ; <i32> [#uses=0] + %C = phi i32 [ %X, %entry ] ; <i32> [#uses=1] + ret i32 %C +} + diff --git a/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll b/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll new file mode 100644 index 0000000..b3c6d8a --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll @@ -0,0 +1,11 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; This testcase failed to work because two variable sized allocas confused the +; local register allocator. + +define i32 @main(i32 %X) { + %A = alloca i32, i32 %X ; <i32*> [#uses=0] + %B = alloca float, i32 %X ; <float*> [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll b/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll new file mode 100644 index 0000000..bd32f30 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll @@ -0,0 +1,21 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; +; Regression Test: EnvironmentTest.ll +; +; Description: +; This is a regression test that verifies that the JIT passes the +; environment to the main() function. +; + + +declare i32 @strlen(i8*) + +define i32 @main(i32 %argc.1, i8** %argv.1, i8** %envp.1) { + %tmp.2 = load i8** %envp.1 ; <i8*> [#uses=1] + %tmp.3 = call i32 @strlen( i8* %tmp.2 ) ; <i32> [#uses=1] + %T = icmp eq i32 %tmp.3, 0 ; <i1> [#uses=1] + %R = zext i1 %T to i32 ; <i32> [#uses=1] + ret i32 %R +} + diff --git a/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll b/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll new file mode 100644 index 0000000..1959534 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll @@ -0,0 +1,34 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; This testcase exposes a bug in the local register allocator where it runs out +; of registers (due to too many overlapping live ranges), but then attempts to +; use the ESP register (which is not allocatable) to hold a value. + +define i32 @main(i32 %A) { + ; ESP gets used again... + %Ap2 = alloca i32, i32 %A ; <i32*> [#uses=11] + ; Produce lots of overlapping live ranges + %B = add i32 %A, 1 ; <i32> [#uses=1] + %C = add i32 %A, 2 ; <i32> [#uses=1] + %D = add i32 %A, 3 ; <i32> [#uses=1] + %E = add i32 %A, 4 ; <i32> [#uses=1] + %F = add i32 %A, 5 ; <i32> [#uses=1] + %G = add i32 %A, 6 ; <i32> [#uses=1] + %H = add i32 %A, 7 ; <i32> [#uses=1] + %I = add i32 %A, 8 ; <i32> [#uses=1] + %J = add i32 %A, 9 ; <i32> [#uses=1] + %K = add i32 %A, 10 ; <i32> [#uses=1] + ; Uses of all of the values + store i32 %A, i32* %Ap2 + store i32 %B, i32* %Ap2 + store i32 %C, i32* %Ap2 + store i32 %D, i32* %Ap2 + store i32 %E, i32* %Ap2 + store i32 %F, i32* %Ap2 + store i32 %G, i32* %Ap2 + store i32 %H, i32* %Ap2 + store i32 %I, i32* %Ap2 + store i32 %J, i32* %Ap2 + store i32 %K, i32* %Ap2 + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll b/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll new file mode 100644 index 0000000..1f8343f --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll @@ -0,0 +1,23 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +@A = global i32 0 ; <i32*> [#uses=1] + +define i32 @main() { + %Ret = call i32 @test( i1 true, i32 0 ) ; <i32> [#uses=1] + ret i32 %Ret +} + +define i32 @test(i1 %c, i32 %A) { + br i1 %c, label %Taken1, label %NotTaken +Cont: ; preds = %Taken1, %NotTaken + %V = phi i32 [ 0, %NotTaken ], [ sub (i32 ptrtoint (i32* @A to i32), i32 1234), %Taken1 ] ; <i32> [#uses=0] + ret i32 0 +NotTaken: ; preds = %0 + br label %Cont +Taken1: ; preds = %0 + %B = icmp eq i32 %A, 0 ; <i1> [#uses=1] + br i1 %B, label %Cont, label %ExitError +ExitError: ; preds = %Taken1 + ret i32 12 +} + diff --git a/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll b/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll new file mode 100644 index 0000000..79a7d58 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll @@ -0,0 +1,22 @@ +; PR672 +; RUN: %lli -use-mcjit %s +; XFAIL: mcjit-ia32 + +define i32 @main() { + %f = bitcast i32 (i32, i32*, i32)* @check_tail to i32* ; <i32*> [#uses=1] + %res = tail call fastcc i32 @check_tail( i32 10, i32* %f, i32 10 ) ; <i32> [#uses=1] + ret i32 %res +} + +define fastcc i32 @check_tail(i32 %x, i32* %f, i32 %g) { + %tmp1 = icmp sgt i32 %x, 0 ; <i1> [#uses=1] + br i1 %tmp1, label %if-then, label %if-else +if-then: ; preds = %0 + %fun_ptr = bitcast i32* %f to i32 (i32, i32*, i32)* ; <i32 (i32, i32*, i32)*> [#uses=1] + %arg1 = add i32 %x, -1 ; <i32> [#uses=1] + %res = tail call fastcc i32 %fun_ptr( i32 %arg1, i32* %f, i32 %g ) ; <i32> [#uses=1] + ret i32 %res +if-else: ; preds = %0 + ret i32 %x +} + diff --git a/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll b/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll new file mode 100644 index 0000000..52cef4d --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll @@ -0,0 +1,19 @@ +; RUN: %lli -use-mcjit -force-interpreter %s +; PR1836 + +define i32 @main() { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %tmp = alloca i32 ; <i32*> [#uses=2] + %x = alloca i75, align 16 ; <i75*> [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i75 999, i75* %x, align 16 + store i32 0, i32* %tmp, align 4 + %tmp1 = load i32* %tmp, align 4 ; <i32> [#uses=1] + store i32 %tmp1, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval2 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval2 +} diff --git a/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll new file mode 100644 index 0000000..a6e917f --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll @@ -0,0 +1,59 @@ +; RUN: %lli -use-mcjit -force-interpreter=true %s | grep 1 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i686-pc-linux-gnu" +@.str = internal constant [10 x i8] c"MSB = %d\0A\00" ; <[10 x i8]*> [#uses=1] + +define i65 @foo(i65 %x) { +entry: + %x_addr = alloca i65 ; <i65*> [#uses=2] + %retval = alloca i65 ; <i65*> [#uses=2] + %tmp = alloca i65 ; <i65*> [#uses=2] + %"alloca point" = bitcast i65 0 to i65 ; <i65> [#uses=0] + store i65 %x, i65* %x_addr + %tmp1 = load i65* %x_addr, align 4 ; <i65> [#uses=1] + %tmp2 = ashr i65 %tmp1, 65 ; <i65> [#uses=1] + store i65 %tmp2, i65* %tmp, align 4 + %tmp3 = load i65* %tmp, align 4 ; <i65> [#uses=1] + store i65 %tmp3, i65* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval4 = load i65* %retval ; <i65> [#uses=1] + ret i65 %retval4 +} + +define i32 @main() { +entry: + %retval = alloca i32 ; <i32*> [#uses=1] + %iftmp.0 = alloca i32 ; <i32*> [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %tmp = call i65 @foo( i65 -9 ) ; <i65> [#uses=1] + %tmp1 = lshr i65 %tmp, 64 ; <i65> [#uses=1] + %tmp2 = xor i65 %tmp1, 1 ; <i65> [#uses=1] + %tmp3 = and i65 %tmp2, 1 ; <i65> [#uses=1] + %tmp34 = trunc i65 %tmp3 to i8 ; <i8> [#uses=1] + %toBool = icmp ne i8 %tmp34, 0 ; <i1> [#uses=1] + br i1 %toBool, label %cond_true, label %cond_false + +cond_true: ; preds = %entry + store i32 0, i32* %iftmp.0, align 4 + br label %cond_next + +cond_false: ; preds = %entry + store i32 1, i32* %iftmp.0, align 4 + br label %cond_next + +cond_next: ; preds = %cond_false, %cond_true + %tmp5 = getelementptr [10 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1] + %tmp6 = load i32* %iftmp.0, align 4 ; <i32> [#uses=1] + %tmp7 = call i32 (i8*, ...)* @printf( i8* noalias %tmp5, i32 %tmp6 ) nounwind ; <i32> [#uses=0] + br label %return + +return: ; preds = %cond_next + store i32 0, i32* %retval, align 4 + %retval8 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval8 +} + +declare i32 @printf(i8* noalias , ...) nounwind diff --git a/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll b/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll new file mode 100644 index 0000000..524a724 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll @@ -0,0 +1,8 @@ +; RUN: %lli -use-mcjit -force-interpreter=true %s + +define i32 @main() { + %a = add i32 0, undef + %b = fadd float 0.0, undef + %c = fadd double 0.0, undef + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/fpbitcast.ll b/test/ExecutionEngine/MCJIT/fpbitcast.ll new file mode 100644 index 0000000..9da908f --- /dev/null +++ b/test/ExecutionEngine/MCJIT/fpbitcast.ll @@ -0,0 +1,20 @@ +; RUN: %lli -use-mcjit -force-interpreter=true %s | grep 40091eb8 +; +define i32 @test(double %x) { +entry: + %x46.i = bitcast double %x to i64 + %tmp343.i = lshr i64 %x46.i, 32 + %tmp344.i = trunc i64 %tmp343.i to i32 + ret i32 %tmp344.i +} + +define i32 @main() +{ + %res = call i32 @test(double 3.14) + %ptr = getelementptr [4 x i8]* @format, i32 0, i32 0 + call i32 (i8*,...)* @printf(i8* %ptr, i32 %res) + ret i32 0 +} + +declare i32 @printf(i8*, ...) +@format = internal constant [4 x i8] c"%x\0A\00" diff --git a/test/ExecutionEngine/MCJIT/hello.ll b/test/ExecutionEngine/MCJIT/hello.ll new file mode 100644 index 0000000..a52b6d4 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/hello.ll @@ -0,0 +1,11 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +@.LC0 = internal global [12 x i8] c"Hello World\00" ; <[12 x i8]*> [#uses=1] + +declare i32 @puts(i8*) + +define i32 @main() { + %reg210 = call i32 @puts( i8* getelementptr ([12 x i8]* @.LC0, i64 0, i64 0) ) ; <i32> [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/hello2.ll b/test/ExecutionEngine/MCJIT/hello2.ll new file mode 100644 index 0000000..670a6dd --- /dev/null +++ b/test/ExecutionEngine/MCJIT/hello2.ll @@ -0,0 +1,17 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +@X = global i32 7 ; <i32*> [#uses=0] +@msg = internal global [13 x i8] c"Hello World\0A\00" ; <[13 x i8]*> [#uses=1] + +declare void @printf([13 x i8]*, ...) + +define void @bar() { + call void ([13 x i8]*, ...)* @printf( [13 x i8]* @msg ) + ret void +} + +define i32 @main() { + call void @bar( ) + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/lit.local.cfg b/test/ExecutionEngine/MCJIT/lit.local.cfg new file mode 100644 index 0000000..f943fe4 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/lit.local.cfg @@ -0,0 +1,17 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +targets = set(root.targets_to_build.split()) +if ('X86' in targets) | ('ARM' in targets): + config.unsupported = False +else: + config.unsupported = True + +if root.host_os in ['Win32', 'Cygwin', 'MingW']: + config.unsupported = True diff --git a/test/ExecutionEngine/MCJIT/simplesttest.ll b/test/ExecutionEngine/MCJIT/simplesttest.ll new file mode 100644 index 0000000..a6688c2 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/simplesttest.ll @@ -0,0 +1,6 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/simpletest.ll b/test/ExecutionEngine/MCJIT/simpletest.ll new file mode 100644 index 0000000..4562aa6 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/simpletest.ll @@ -0,0 +1,11 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @bar() { + ret i32 0 +} + +define i32 @main() { + %r = call i32 @bar( ) ; <i32> [#uses=1] + ret i32 %r +} + diff --git a/test/ExecutionEngine/MCJIT/test-arith.ll b/test/ExecutionEngine/MCJIT/test-arith.ll new file mode 100644 index 0000000..3177760 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-arith.ll @@ -0,0 +1,34 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { + %A = add i8 0, 12 ; <i8> [#uses=1] + %B = sub i8 %A, 1 ; <i8> [#uses=2] + %C = mul i8 %B, %B ; <i8> [#uses=2] + %D = sdiv i8 %C, %C ; <i8> [#uses=2] + %E = srem i8 %D, %D ; <i8> [#uses=0] + %F = udiv i8 5, 6 ; <i8> [#uses=0] + %G = urem i8 6, 5 ; <i8> [#uses=0] + %A.upgrd.1 = add i16 0, 12 ; <i16> [#uses=1] + %B.upgrd.2 = sub i16 %A.upgrd.1, 1 ; <i16> [#uses=2] + %C.upgrd.3 = mul i16 %B.upgrd.2, %B.upgrd.2 ; <i16> [#uses=2] + %D.upgrd.4 = sdiv i16 %C.upgrd.3, %C.upgrd.3 ; <i16> [#uses=2] + %E.upgrd.5 = srem i16 %D.upgrd.4, %D.upgrd.4 ; <i16> [#uses=0] + %F.upgrd.6 = udiv i16 5, 6 ; <i16> [#uses=0] + %G.upgrd.7 = urem i32 6, 5 ; <i32> [#uses=0] + %A.upgrd.8 = add i32 0, 12 ; <i32> [#uses=1] + %B.upgrd.9 = sub i32 %A.upgrd.8, 1 ; <i32> [#uses=2] + %C.upgrd.10 = mul i32 %B.upgrd.9, %B.upgrd.9 ; <i32> [#uses=2] + %D.upgrd.11 = sdiv i32 %C.upgrd.10, %C.upgrd.10 ; <i32> [#uses=2] + %E.upgrd.12 = srem i32 %D.upgrd.11, %D.upgrd.11 ; <i32> [#uses=0] + %F.upgrd.13 = udiv i32 5, 6 ; <i32> [#uses=0] + %G1 = urem i32 6, 5 ; <i32> [#uses=0] + %A.upgrd.14 = add i64 0, 12 ; <i64> [#uses=1] + %B.upgrd.15 = sub i64 %A.upgrd.14, 1 ; <i64> [#uses=2] + %C.upgrd.16 = mul i64 %B.upgrd.15, %B.upgrd.15 ; <i64> [#uses=2] + %D.upgrd.17 = sdiv i64 %C.upgrd.16, %C.upgrd.16 ; <i64> [#uses=2] + %E.upgrd.18 = srem i64 %D.upgrd.17, %D.upgrd.17 ; <i64> [#uses=0] + %F.upgrd.19 = udiv i64 5, 6 ; <i64> [#uses=0] + %G.upgrd.20 = urem i64 6, 5 ; <i64> [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/test-branch.ll b/test/ExecutionEngine/MCJIT/test-branch.ll new file mode 100644 index 0000000..702c110 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-branch.ll @@ -0,0 +1,12 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; test unconditional branch +define i32 @main() { + br label %Test +Test: ; preds = %Test, %0 + %X = icmp eq i32 0, 4 ; <i1> [#uses=1] + br i1 %X, label %Test, label %Label +Label: ; preds = %Test + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll b/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll new file mode 100644 index 0000000..6f28405 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll @@ -0,0 +1,14 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @_Z14func_exit_codev() nounwind uwtable { +entry: + ret i32 0 +} + +define i32 @main() nounwind uwtable { +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %call = call i32 @_Z14func_exit_codev() + ret i32 %call +} diff --git a/test/ExecutionEngine/MCJIT/test-call.ll b/test/ExecutionEngine/MCJIT/test-call.ll new file mode 100644 index 0000000..7a244ee --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-call.ll @@ -0,0 +1,21 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +declare void @exit(i32) + +define i32 @test(i8 %C, i16 %S) { + %X = trunc i16 %S to i8 ; <i8> [#uses=1] + %Y = zext i8 %X to i32 ; <i32> [#uses=1] + ret i32 %Y +} + +define void @FP(void (i32)* %F) { + %X = call i32 @test( i8 123, i16 1024 ) ; <i32> [#uses=1] + call void %F( i32 %X ) + ret void +} + +define i32 @main() { + call void @FP( void (i32)* @exit ) + ret i32 1 +} + diff --git a/test/ExecutionEngine/MCJIT/test-cast.ll b/test/ExecutionEngine/MCJIT/test-cast.ll new file mode 100644 index 0000000..75e7d1b --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-cast.ll @@ -0,0 +1,109 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @foo() { + ret i32 0 +} + +define i32 @main() { + icmp ne i1 true, false ; <i1>:1 [#uses=0] + zext i1 true to i8 ; <i8>:2 [#uses=0] + zext i1 true to i8 ; <i8>:3 [#uses=0] + zext i1 true to i16 ; <i16>:4 [#uses=0] + zext i1 true to i16 ; <i16>:5 [#uses=0] + zext i1 true to i32 ; <i32>:6 [#uses=0] + zext i1 true to i32 ; <i32>:7 [#uses=0] + zext i1 true to i64 ; <i64>:8 [#uses=0] + zext i1 true to i64 ; <i64>:9 [#uses=0] + uitofp i1 true to float ; <float>:10 [#uses=0] + uitofp i1 true to double ; <double>:11 [#uses=0] + icmp ne i8 0, 0 ; <i1>:12 [#uses=0] + icmp ne i8 1, 0 ; <i1>:13 [#uses=0] + bitcast i8 0 to i8 ; <i8>:14 [#uses=0] + bitcast i8 -1 to i8 ; <i8>:15 [#uses=0] + sext i8 4 to i16 ; <i16>:16 [#uses=0] + sext i8 4 to i16 ; <i16>:17 [#uses=0] + sext i8 4 to i64 ; <i64>:18 [#uses=0] + sext i8 4 to i64 ; <i64>:19 [#uses=0] + sitofp i8 4 to float ; <float>:20 [#uses=0] + sitofp i8 4 to double ; <double>:21 [#uses=0] + icmp ne i8 0, 0 ; <i1>:22 [#uses=0] + icmp ne i8 1, 0 ; <i1>:23 [#uses=0] + bitcast i8 0 to i8 ; <i8>:24 [#uses=0] + bitcast i8 1 to i8 ; <i8>:25 [#uses=0] + zext i8 4 to i16 ; <i16>:26 [#uses=0] + zext i8 4 to i16 ; <i16>:27 [#uses=0] + zext i8 4 to i64 ; <i64>:28 [#uses=0] + zext i8 4 to i64 ; <i64>:29 [#uses=0] + uitofp i8 0 to float ; <float>:30 [#uses=0] + uitofp i8 0 to double ; <double>:31 [#uses=0] + icmp ne i16 1, 0 ; <i1>:32 [#uses=0] + trunc i16 -1 to i8 ; <i8>:33 [#uses=0] + trunc i16 255 to i8 ; <i8>:34 [#uses=0] + bitcast i16 0 to i16 ; <i16>:35 [#uses=0] + bitcast i16 0 to i16 ; <i16>:36 [#uses=0] + sext i16 0 to i64 ; <i64>:37 [#uses=0] + sext i16 0 to i64 ; <i64>:38 [#uses=0] + sitofp i16 0 to float ; <float>:39 [#uses=0] + sitofp i16 0 to double ; <double>:40 [#uses=0] + icmp ne i16 1, 0 ; <i1>:41 [#uses=0] + trunc i16 1 to i8 ; <i8>:42 [#uses=0] + trunc i16 255 to i8 ; <i8>:43 [#uses=0] + bitcast i16 0 to i16 ; <i16>:44 [#uses=0] + bitcast i16 0 to i16 ; <i16>:45 [#uses=0] + zext i16 0 to i64 ; <i64>:46 [#uses=0] + zext i16 0 to i64 ; <i64>:47 [#uses=0] + uitofp i16 0 to float ; <float>:48 [#uses=0] + uitofp i16 0 to double ; <double>:49 [#uses=0] + icmp ne i32 6, 0 ; <i1>:50 [#uses=0] + trunc i32 -6 to i8 ; <i8>:51 [#uses=0] + trunc i32 6 to i8 ; <i8>:52 [#uses=0] + trunc i32 6 to i16 ; <i16>:53 [#uses=0] + bitcast i32 0 to i32 ; <i32>:54 [#uses=0] + sext i32 0 to i64 ; <i64>:55 [#uses=0] + sext i32 0 to i64 ; <i64>:56 [#uses=0] + sitofp i32 0 to float ; <float>:57 [#uses=0] + sitofp i32 0 to double ; <double>:58 [#uses=0] + icmp ne i32 6, 0 ; <i1>:59 [#uses=0] + trunc i32 7 to i8 ; <i8>:60 [#uses=0] + trunc i32 8 to i8 ; <i8>:61 [#uses=0] + trunc i32 9 to i16 ; <i16>:62 [#uses=0] + bitcast i32 10 to i32 ; <i32>:63 [#uses=0] + zext i32 0 to i64 ; <i64>:64 [#uses=0] + zext i32 0 to i64 ; <i64>:65 [#uses=0] + uitofp i32 0 to float ; <float>:66 [#uses=0] + uitofp i32 0 to double ; <double>:67 [#uses=0] + icmp ne i64 0, 0 ; <i1>:68 [#uses=0] + trunc i64 0 to i8 ; <i8>:69 [#uses=0] + trunc i64 0 to i8 ; <i8>:70 [#uses=0] + trunc i64 0 to i16 ; <i16>:71 [#uses=0] + trunc i64 0 to i16 ; <i16>:72 [#uses=0] + trunc i64 0 to i32 ; <i32>:73 [#uses=0] + trunc i64 0 to i32 ; <i32>:74 [#uses=0] + bitcast i64 0 to i64 ; <i64>:75 [#uses=0] + bitcast i64 0 to i64 ; <i64>:76 [#uses=0] + sitofp i64 0 to float ; <float>:77 [#uses=0] + sitofp i64 0 to double ; <double>:78 [#uses=0] + icmp ne i64 1, 0 ; <i1>:79 [#uses=0] + trunc i64 1 to i8 ; <i8>:80 [#uses=0] + trunc i64 1 to i8 ; <i8>:81 [#uses=0] + trunc i64 1 to i16 ; <i16>:82 [#uses=0] + trunc i64 1 to i16 ; <i16>:83 [#uses=0] + trunc i64 1 to i32 ; <i32>:84 [#uses=0] + trunc i64 1 to i32 ; <i32>:85 [#uses=0] + bitcast i64 1 to i64 ; <i64>:86 [#uses=0] + bitcast i64 1 to i64 ; <i64>:87 [#uses=0] + uitofp i64 1 to float ; <float>:88 [#uses=0] + uitofp i64 0 to double ; <double>:89 [#uses=0] + bitcast float 0.000000e+00 to float ; <float>:90 [#uses=0] + fpext float 0.000000e+00 to double ; <double>:91 [#uses=0] + fptosi double 0.000000e+00 to i8 ; <i8>:92 [#uses=0] + fptoui double 0.000000e+00 to i8 ; <i8>:93 [#uses=0] + fptosi double 0.000000e+00 to i16 ; <i16>:94 [#uses=0] + fptoui double 0.000000e+00 to i16 ; <i16>:95 [#uses=0] + fptosi double 0.000000e+00 to i32 ; <i32>:96 [#uses=0] + fptoui double 0.000000e+00 to i32 ; <i32>:97 [#uses=0] + fptosi double 0.000000e+00 to i64 ; <i64>:98 [#uses=0] + fptrunc double 0.000000e+00 to float ; <float>:99 [#uses=0] + bitcast double 0.000000e+00 to double ; <double>:100 [#uses=0] + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/test-constantexpr.ll b/test/ExecutionEngine/MCJIT/test-constantexpr.ll new file mode 100644 index 0000000..6b46639 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-constantexpr.ll @@ -0,0 +1,12 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; This tests to make sure that we can evaluate weird constant expressions + +@A = global i32 5 ; <i32*> [#uses=1] +@B = global i32 6 ; <i32*> [#uses=1] + +define i32 @main() { + %A = or i1 false, icmp slt (i32* @A, i32* @B) ; <i1> [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll b/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll new file mode 100644 index 0000000..35491df --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll @@ -0,0 +1,21 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define double @test(double* %DP, double %Arg) { + %D = load double* %DP ; <double> [#uses=1] + %V = fadd double %D, 1.000000e+00 ; <double> [#uses=2] + %W = fsub double %V, %V ; <double> [#uses=3] + %X = fmul double %W, %W ; <double> [#uses=2] + %Y = fdiv double %X, %X ; <double> [#uses=2] + %Q = fadd double %Y, %Arg ; <double> [#uses=1] + %R = bitcast double %Q to double ; <double> [#uses=1] + store double %Q, double* %DP + ret double %Y +} + +define i32 @main() { + %X = alloca double ; <double*> [#uses=2] + store double 0.000000e+00, double* %X + call double @test( double* %X, double 2.000000e+00 ) ; <double>:1 [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/test-fp.ll b/test/ExecutionEngine/MCJIT/test-fp.ll new file mode 100644 index 0000000..6fc5a50 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-fp.ll @@ -0,0 +1,23 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define double @test(double* %DP, double %Arg) { + %D = load double* %DP ; <double> [#uses=1] + %V = fadd double %D, 1.000000e+00 ; <double> [#uses=2] + %W = fsub double %V, %V ; <double> [#uses=3] + %X = fmul double %W, %W ; <double> [#uses=2] + %Y = fdiv double %X, %X ; <double> [#uses=2] + %Z = frem double %Y, %Y ; <double> [#uses=3] + %Z1 = fdiv double %Z, %W ; <double> [#uses=0] + %Q = fadd double %Z, %Arg ; <double> [#uses=1] + %R = bitcast double %Q to double ; <double> [#uses=1] + store double %R, double* %DP + ret double %Z +} + +define i32 @main() { + %X = alloca double ; <double*> [#uses=2] + store double 0.000000e+00, double* %X + call double @test( double* %X, double 2.000000e+00 ) ; <double>:1 [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll b/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll new file mode 100644 index 0000000..4a790c6 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll @@ -0,0 +1,34 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +@count = global i32 1, align 4 + +define i32 @main() nounwind uwtable { +entry: + %retval = alloca i32, align 4 + %i = alloca i32, align 4 + store i32 0, i32* %retval + store i32 0, i32* %i, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %0 = load i32* %i, align 4 + %cmp = icmp slt i32 %0, 49 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %1 = load i32* @count, align 4 + %inc = add nsw i32 %1, 1 + store i32 %inc, i32* @count, align 4 + br label %for.inc + +for.inc: ; preds = %for.body + %2 = load i32* %i, align 4 + %inc1 = add nsw i32 %2, 1 + store i32 %inc1, i32* %i, align 4 + br label %for.cond + +for.end: ; preds = %for.cond + %3 = load i32* @count, align 4 + %sub = sub nsw i32 %3, 50 + ret i32 %sub +} diff --git a/test/ExecutionEngine/MCJIT/test-loadstore.ll b/test/ExecutionEngine/MCJIT/test-loadstore.ll new file mode 100644 index 0000000..e917149 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-loadstore.ll @@ -0,0 +1,31 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) { + %V = load i8* %P ; <i8> [#uses=1] + store i8 %V, i8* %P + %V.upgrd.4 = load i16* %P.upgrd.1 ; <i16> [#uses=1] + store i16 %V.upgrd.4, i16* %P.upgrd.1 + %V.upgrd.5 = load i32* %P.upgrd.2 ; <i32> [#uses=1] + store i32 %V.upgrd.5, i32* %P.upgrd.2 + %V.upgrd.6 = load i64* %P.upgrd.3 ; <i64> [#uses=1] + store i64 %V.upgrd.6, i64* %P.upgrd.3 + ret void +} + +define i32 @varalloca(i32 %Size) { + ;; Variable sized alloca + %X = alloca i32, i32 %Size ; <i32*> [#uses=2] + store i32 %Size, i32* %X + %Y = load i32* %X ; <i32> [#uses=1] + ret i32 %Y +} + +define i32 @main() { + %A = alloca i8 ; <i8*> [#uses=1] + %B = alloca i16 ; <i16*> [#uses=1] + %C = alloca i32 ; <i32*> [#uses=1] + %D = alloca i64 ; <i64*> [#uses=1] + call void @test( i8* %A, i16* %B, i32* %C, i64* %D ) + call i32 @varalloca( i32 7 ) ; <i32>:1 [#uses=0] + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/test-local.ll b/test/ExecutionEngine/MCJIT/test-local.ll new file mode 100644 index 0000000..4f5ae47 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-local.ll @@ -0,0 +1,34 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() nounwind uwtable { +entry: + %retval = alloca i32, align 4 + %count = alloca i32, align 4 + %i = alloca i32, align 4 + store i32 0, i32* %retval + store i32 0, i32* %count, align 4 + store i32 0, i32* %i, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %0 = load i32* %i, align 4 + %cmp = icmp slt i32 %0, 50 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %1 = load i32* %count, align 4 + %inc = add nsw i32 %1, 1 + store i32 %inc, i32* %count, align 4 + br label %for.inc + +for.inc: ; preds = %for.body + %2 = load i32* %i, align 4 + %inc1 = add nsw i32 %2, 1 + store i32 %inc1, i32* %i, align 4 + br label %for.cond + +for.end: ; preds = %for.cond + %3 = load i32* %count, align 4 + %sub = sub nsw i32 %3, 50 + ret i32 %sub +} diff --git a/test/ExecutionEngine/MCJIT/test-logical.ll b/test/ExecutionEngine/MCJIT/test-logical.ll new file mode 100644 index 0000000..0540c22 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-logical.ll @@ -0,0 +1,18 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { + %A = and i8 4, 8 ; <i8> [#uses=2] + %B = or i8 %A, 7 ; <i8> [#uses=1] + %C = xor i8 %B, %A ; <i8> [#uses=0] + %A.upgrd.1 = and i16 4, 8 ; <i16> [#uses=2] + %B.upgrd.2 = or i16 %A.upgrd.1, 7 ; <i16> [#uses=1] + %C.upgrd.3 = xor i16 %B.upgrd.2, %A.upgrd.1 ; <i16> [#uses=0] + %A.upgrd.4 = and i32 4, 8 ; <i32> [#uses=2] + %B.upgrd.5 = or i32 %A.upgrd.4, 7 ; <i32> [#uses=1] + %C.upgrd.6 = xor i32 %B.upgrd.5, %A.upgrd.4 ; <i32> [#uses=0] + %A.upgrd.7 = and i64 4, 8 ; <i64> [#uses=2] + %B.upgrd.8 = or i64 %A.upgrd.7, 7 ; <i64> [#uses=1] + %C.upgrd.9 = xor i64 %B.upgrd.8, %A.upgrd.7 ; <i64> [#uses=0] + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/test-loop.ll b/test/ExecutionEngine/MCJIT/test-loop.ll new file mode 100644 index 0000000..b1dbf40 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-loop.ll @@ -0,0 +1,14 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { +; <label>:0 + br label %Loop +Loop: ; preds = %Loop, %0 + %I = phi i32 [ 0, %0 ], [ %i2, %Loop ] ; <i32> [#uses=1] + %i2 = add i32 %I, 1 ; <i32> [#uses=2] + %C = icmp eq i32 %i2, 10 ; <i1> [#uses=1] + br i1 %C, label %Out, label %Loop +Out: ; preds = %Loop + ret i32 0 +} + diff --git a/test/ExecutionEngine/MCJIT/test-phi.ll b/test/ExecutionEngine/MCJIT/test-phi.ll new file mode 100644 index 0000000..fbc0808 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-phi.ll @@ -0,0 +1,34 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; test phi node +@Y = global i32 6 ; <i32*> [#uses=1] + +define void @blah(i32* %X) { +; <label>:0 + br label %T +T: ; preds = %Dead, %0 + phi i32* [ %X, %0 ], [ @Y, %Dead ] ; <i32*>:1 [#uses=0] + ret void +Dead: ; No predecessors! + br label %T +} + +define i32 @test(i1 %C) { +; <label>:0 + br i1 %C, label %T, label %T +T: ; preds = %0, %0 + %X = phi i32 [ 123, %0 ], [ 123, %0 ] ; <i32> [#uses=1] + ret i32 %X +} + +define i32 @main() { +; <label>:0 + br label %Test +Test: ; preds = %Dead, %0 + %X = phi i32 [ 0, %0 ], [ %Y, %Dead ] ; <i32> [#uses=1] + ret i32 %X +Dead: ; No predecessors! + %Y = ashr i32 12, 4 ; <i32> [#uses=1] + br label %Test +} + diff --git a/test/ExecutionEngine/MCJIT/test-ret.ll b/test/ExecutionEngine/MCJIT/test-ret.ll new file mode 100644 index 0000000..1b90ee0 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-ret.ll @@ -0,0 +1,46 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +; test return instructions +define void @test1() { + ret void +} + +define i8 @test2() { + ret i8 1 +} + +define i8 @test3() { + ret i8 1 +} + +define i16 @test4() { + ret i16 -1 +} + +define i16 @test5() { + ret i16 -1 +} + +define i32 @main() { + ret i32 0 +} + +define i32 @test6() { + ret i32 4 +} + +define i64 @test7() { + ret i64 0 +} + +define i64 @test8() { + ret i64 0 +} + +define float @test9() { + ret float 1.000000e+00 +} + +define double @test10() { + ret double 2.000000e+00 +} diff --git a/test/ExecutionEngine/MCJIT/test-return.ll b/test/ExecutionEngine/MCJIT/test-return.ll new file mode 100644 index 0000000..9c399ca --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-return.ll @@ -0,0 +1,8 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() nounwind uwtable { +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/test-setcond-fp.ll b/test/ExecutionEngine/MCJIT/test-setcond-fp.ll new file mode 100644 index 0000000..030ff31 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-setcond-fp.ll @@ -0,0 +1,24 @@ +; RUN: %lli -use-mcjit %s > /dev/null + + +define i32 @main() { + %double1 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=6] + %double2 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=6] + %float1 = fadd float 0.000000e+00, 0.000000e+00 ; <float> [#uses=6] + %float2 = fadd float 0.000000e+00, 0.000000e+00 ; <float> [#uses=6] + %test49 = fcmp oeq float %float1, %float2 ; <i1> [#uses=0] + %test50 = fcmp oge float %float1, %float2 ; <i1> [#uses=0] + %test51 = fcmp ogt float %float1, %float2 ; <i1> [#uses=0] + %test52 = fcmp ole float %float1, %float2 ; <i1> [#uses=0] + %test53 = fcmp olt float %float1, %float2 ; <i1> [#uses=0] + %test54 = fcmp une float %float1, %float2 ; <i1> [#uses=0] + %test55 = fcmp oeq double %double1, %double2 ; <i1> [#uses=0] + %test56 = fcmp oge double %double1, %double2 ; <i1> [#uses=0] + %test57 = fcmp ogt double %double1, %double2 ; <i1> [#uses=0] + %test58 = fcmp ole double %double1, %double2 ; <i1> [#uses=0] + %test59 = fcmp olt double %double1, %double2 ; <i1> [#uses=0] + %test60 = fcmp une double %double1, %double2 ; <i1> [#uses=0] + ret i32 0 +} + + diff --git a/test/ExecutionEngine/MCJIT/test-setcond-int.ll b/test/ExecutionEngine/MCJIT/test-setcond-int.ll new file mode 100644 index 0000000..1113efe --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-setcond-int.ll @@ -0,0 +1,69 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { + %int1 = add i32 0, 0 ; <i32> [#uses=6] + %int2 = add i32 0, 0 ; <i32> [#uses=6] + %long1 = add i64 0, 0 ; <i64> [#uses=6] + %long2 = add i64 0, 0 ; <i64> [#uses=6] + %sbyte1 = add i8 0, 0 ; <i8> [#uses=6] + %sbyte2 = add i8 0, 0 ; <i8> [#uses=6] + %short1 = add i16 0, 0 ; <i16> [#uses=6] + %short2 = add i16 0, 0 ; <i16> [#uses=6] + %ubyte1 = add i8 0, 0 ; <i8> [#uses=6] + %ubyte2 = add i8 0, 0 ; <i8> [#uses=6] + %uint1 = add i32 0, 0 ; <i32> [#uses=6] + %uint2 = add i32 0, 0 ; <i32> [#uses=6] + %ulong1 = add i64 0, 0 ; <i64> [#uses=6] + %ulong2 = add i64 0, 0 ; <i64> [#uses=6] + %ushort1 = add i16 0, 0 ; <i16> [#uses=6] + %ushort2 = add i16 0, 0 ; <i16> [#uses=6] + %test1 = icmp eq i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] + %test2 = icmp uge i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] + %test3 = icmp ugt i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] + %test4 = icmp ule i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] + %test5 = icmp ult i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] + %test6 = icmp ne i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] + %test7 = icmp eq i16 %ushort1, %ushort2 ; <i1> [#uses=0] + %test8 = icmp uge i16 %ushort1, %ushort2 ; <i1> [#uses=0] + %test9 = icmp ugt i16 %ushort1, %ushort2 ; <i1> [#uses=0] + %test10 = icmp ule i16 %ushort1, %ushort2 ; <i1> [#uses=0] + %test11 = icmp ult i16 %ushort1, %ushort2 ; <i1> [#uses=0] + %test12 = icmp ne i16 %ushort1, %ushort2 ; <i1> [#uses=0] + %test13 = icmp eq i32 %uint1, %uint2 ; <i1> [#uses=0] + %test14 = icmp uge i32 %uint1, %uint2 ; <i1> [#uses=0] + %test15 = icmp ugt i32 %uint1, %uint2 ; <i1> [#uses=0] + %test16 = icmp ule i32 %uint1, %uint2 ; <i1> [#uses=0] + %test17 = icmp ult i32 %uint1, %uint2 ; <i1> [#uses=0] + %test18 = icmp ne i32 %uint1, %uint2 ; <i1> [#uses=0] + %test19 = icmp eq i64 %ulong1, %ulong2 ; <i1> [#uses=0] + %test20 = icmp uge i64 %ulong1, %ulong2 ; <i1> [#uses=0] + %test21 = icmp ugt i64 %ulong1, %ulong2 ; <i1> [#uses=0] + %test22 = icmp ule i64 %ulong1, %ulong2 ; <i1> [#uses=0] + %test23 = icmp ult i64 %ulong1, %ulong2 ; <i1> [#uses=0] + %test24 = icmp ne i64 %ulong1, %ulong2 ; <i1> [#uses=0] + %test25 = icmp eq i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] + %test26 = icmp sge i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] + %test27 = icmp sgt i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] + %test28 = icmp sle i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] + %test29 = icmp slt i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] + %test30 = icmp ne i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] + %test31 = icmp eq i16 %short1, %short2 ; <i1> [#uses=0] + %test32 = icmp sge i16 %short1, %short2 ; <i1> [#uses=0] + %test33 = icmp sgt i16 %short1, %short2 ; <i1> [#uses=0] + %test34 = icmp sle i16 %short1, %short2 ; <i1> [#uses=0] + %test35 = icmp slt i16 %short1, %short2 ; <i1> [#uses=0] + %test36 = icmp ne i16 %short1, %short2 ; <i1> [#uses=0] + %test37 = icmp eq i32 %int1, %int2 ; <i1> [#uses=0] + %test38 = icmp sge i32 %int1, %int2 ; <i1> [#uses=0] + %test39 = icmp sgt i32 %int1, %int2 ; <i1> [#uses=0] + %test40 = icmp sle i32 %int1, %int2 ; <i1> [#uses=0] + %test41 = icmp slt i32 %int1, %int2 ; <i1> [#uses=0] + %test42 = icmp ne i32 %int1, %int2 ; <i1> [#uses=0] + %test43 = icmp eq i64 %long1, %long2 ; <i1> [#uses=0] + %test44 = icmp sge i64 %long1, %long2 ; <i1> [#uses=0] + %test45 = icmp sgt i64 %long1, %long2 ; <i1> [#uses=0] + %test46 = icmp sle i64 %long1, %long2 ; <i1> [#uses=0] + %test47 = icmp slt i64 %long1, %long2 ; <i1> [#uses=0] + %test48 = icmp ne i64 %long1, %long2 ; <i1> [#uses=0] + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/test-shift.ll b/test/ExecutionEngine/MCJIT/test-shift.ll new file mode 100644 index 0000000..2da824f --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-shift.ll @@ -0,0 +1,32 @@ +; RUN: %lli -use-mcjit %s > /dev/null + +define i32 @main() { + %shamt = add i8 0, 1 ; <i8> [#uses=8] + %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1] + %t1.s = shl i32 1, %shift.upgrd.1 ; <i32> [#uses=0] + %t2.s = shl i32 1, 4 ; <i32> [#uses=0] + %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1] + %t1 = shl i32 1, %shift.upgrd.2 ; <i32> [#uses=0] + %t2 = shl i32 1, 5 ; <i32> [#uses=0] + %t2.s.upgrd.3 = shl i64 1, 4 ; <i64> [#uses=0] + %t2.upgrd.4 = shl i64 1, 5 ; <i64> [#uses=0] + %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1] + %tr1.s = ashr i32 1, %shift.upgrd.5 ; <i32> [#uses=0] + %tr2.s = ashr i32 1, 4 ; <i32> [#uses=0] + %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1] + %tr1 = lshr i32 1, %shift.upgrd.6 ; <i32> [#uses=0] + %tr2 = lshr i32 1, 5 ; <i32> [#uses=0] + %tr1.l = ashr i64 1, 4 ; <i64> [#uses=0] + %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1] + %tr2.l = ashr i64 1, %shift.upgrd.7 ; <i64> [#uses=0] + %tr3.l = shl i64 1, 4 ; <i64> [#uses=0] + %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1] + %tr4.l = shl i64 1, %shift.upgrd.8 ; <i64> [#uses=0] + %tr1.u = lshr i64 1, 5 ; <i64> [#uses=0] + %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1] + %tr2.u = lshr i64 1, %shift.upgrd.9 ; <i64> [#uses=0] + %tr3.u = shl i64 1, 5 ; <i64> [#uses=0] + %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1] + %tr4.u = shl i64 1, %shift.upgrd.10 ; <i64> [#uses=0] + ret i32 0 +} diff --git a/test/Instrumentation/AddressSanitizer/bug_11395.ll b/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll index 35c5c4a..35c5c4a 100644 --- a/test/Instrumentation/AddressSanitizer/bug_11395.ll +++ b/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll diff --git a/test/Instrumentation/AddressSanitizer/X86/lit.local.cfg b/test/Instrumentation/AddressSanitizer/X86/lit.local.cfg new file mode 100644 index 0000000..b05ed3c --- /dev/null +++ b/test/Instrumentation/AddressSanitizer/X86/lit.local.cfg @@ -0,0 +1,13 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +targets = set(root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True + diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 78311af..ce97ca6 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -1084,9 +1084,13 @@ _func: @------------------------------------------------------------------------------ mcr p7, #1, r5, c1, c1, #4 mcr2 p7, #1, r5, c1, c1, #4 + mcr p14, #0, r4, c0, c5 + mcr2 p4, #2, r2, c1, c3 @ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57] @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57] +@ CHECK: mcr p14, #0, r4, c0, c5, #0 @ encoding: [0x00,0xee,0x15,0x4e] +@ CHECK: mcr2 p4, #2, r2, c1, c3, #0 @ encoding: [0x41,0xfe,0x13,0x24] @------------------------------------------------------------------------------ @@ -1206,9 +1210,13 @@ _func: @------------------------------------------------------------------------------ mrc p14, #0, r1, c1, c2, #4 mrc2 p14, #0, r1, c1, c2, #4 + mrc p11, #1, r1, c2, c2 + mrc2 p12, #3, r3, c3, c4 @ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e] +@ CHECK: mrc p11, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x1b] +@ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index f722dd7..7da79c3 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -216,7 +216,7 @@ @ Out of order STM registers stmda sp!, {r5, r2} -@ CHECK-ERRORS: error: register list not in ascending order +@ CHECK-ERRORS: warning: register list not in ascending order @ CHECK-ERRORS: stmda sp!, {r5, r2} @ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s index 2b14d37..1f07461 100644 --- a/test/MC/ARM/neon-vst-encoding.s +++ b/test/MC/ARM/neon-vst-encoding.s @@ -264,3 +264,7 @@ @ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] @ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] @ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4] + +@ rdar://11082188 + vst2.8 {d8, d10}, [r4] +@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4] diff --git a/test/MC/ARM/neont2-vst-encoding.s b/test/MC/ARM/neont2-vst-encoding.s index 1722f12..b50d8b6 100644 --- a/test/MC/ARM/neont2-vst-encoding.s +++ b/test/MC/ARM/neont2-vst-encoding.s @@ -101,3 +101,7 @@ vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9] vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +@ rdar://11082188 + vst2.8 {d8, d10}, [r4] +@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x04,0xf9,0x0f,0x89] diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index a40e02b..b592f1e 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -120,10 +120,21 @@ @ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] vnmls.f32 s1, s2, s0 -@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] -@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] + vmrs APSR_nzcv, fpscr vmrs apsr_nzcv, fpscr fmstat + vmrs r2, fpsid + vmrs r3, FPSID + vmrs r4, mvfr0 + vmrs r5, MVFR1 + +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee] +@ CHECK: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee] +@ CHECK: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee] +@ CHECK: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee] @ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] vnegne.f64 d16, d16 @@ -302,15 +313,40 @@ @ VCVT (between floating-point and fixed-point) - vcvt.f32.u32 s0, s0, #20 + vcvt.f32.u32 s0, s0, #20 vcvt.f64.s32 d0, d0, #32 vcvt.f32.u16 s0, s0, #1 vcvt.f64.s16 d0, d0, #16 + vcvt.f32.s32 s1, s1, #20 + vcvt.f64.u32 d20, d20, #32 + vcvt.f32.s16 s17, s17, #1 + vcvt.f64.u16 d23, d23, #16 + vcvt.u32.f32 s12, s12, #20 + vcvt.s32.f64 d2, d2, #32 + vcvt.u16.f32 s28, s28, #1 + vcvt.s16.f64 d15, d15, #16 + vcvt.s32.f32 s1, s1, #20 + vcvt.u32.f64 d20, d20, #32 + vcvt.s16.f32 s17, s17, #1 + vcvt.u16.f64 d23, d23, #16 @ CHECK: vcvt.f32.u32 s0, s0, #20 @ encoding: [0xc6,0x0a,0xbb,0xee] @ CHECK: vcvt.f64.s32 d0, d0, #32 @ encoding: [0xc0,0x0b,0xba,0xee] @ CHECK: vcvt.f32.u16 s0, s0, #1 @ encoding: [0x67,0x0a,0xbb,0xee] @ CHECK: vcvt.f64.s16 d0, d0, #16 @ encoding: [0x40,0x0b,0xba,0xee] +@ CHECK: vcvt.f32.s32 s1, s1, #20 @ encoding: [0xc6,0x0a,0xfa,0xee] +@ CHECK: vcvt.f64.u32 d20, d20, #32 @ encoding: [0xc0,0x4b,0xfb,0xee] +@ CHECK: vcvt.f32.s16 s17, s17, #1 @ encoding: [0x67,0x8a,0xfa,0xee] +@ CHECK: vcvt.f64.u16 d23, d23, #16 @ encoding: [0x40,0x7b,0xfb,0xee] + +@ CHECK: vcvt.u32.f32 s12, s12, #20 @ encoding: [0xc6,0x6a,0xbf,0xee] +@ CHECK: vcvt.s32.f64 d2, d2, #32 @ encoding: [0xc0,0x2b,0xbe,0xee] +@ CHECK: vcvt.u16.f32 s28, s28, #1 @ encoding: [0x67,0xea,0xbf,0xee] +@ CHECK: vcvt.s16.f64 d15, d15, #16 @ encoding: [0x40,0xfb,0xbe,0xee] +@ CHECK: vcvt.s32.f32 s1, s1, #20 @ encoding: [0xc6,0x0a,0xfe,0xee] +@ CHECK: vcvt.u32.f64 d20, d20, #32 @ encoding: [0xc0,0x4b,0xff,0xee] +@ CHECK: vcvt.s16.f32 s17, s17, #1 @ encoding: [0x67,0x8a,0xfe,0xee] +@ CHECK: vcvt.u16.f64 d23, d23, #16 @ encoding: [0x40,0x7b,0xff,0xee] @ Use NEON to load some f32 immediates that don't fit the f8 representation. diff --git a/test/MC/ARM/vpush-vpop.s b/test/MC/ARM/vpush-vpop.s index 1212c83..4fb4dec 100644 --- a/test/MC/ARM/vpush-vpop.s +++ b/test/MC/ARM/vpush-vpop.s @@ -7,6 +7,21 @@ foo: vpush {s8, s9, s10, s11, s12} vpop {d8, d9, d10, d11, d12} vpop {s8, s9, s10, s11, s12} +@ optional size suffix + vpush.s8 {d8, d9, d10, d11, d12} + vpush.16 {s8, s9, s10, s11, s12} + vpop.f32 {d8, d9, d10, d11, d12} + vpop.64 {s8, s9, s10, s11, s12} + +@ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b] +@ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a] +@ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b] +@ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a] + +@ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed] +@ CHECK-ARM: vpush {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0x2d,0xed] +@ CHECK-ARM: vpop {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0xbd,0xec] +@ CHECK-ARM: vpop {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0xbd,0xec] @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b] @ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a] diff --git a/test/MC/AsmParser/macro-args.s b/test/MC/AsmParser/macro-args.s index 808b6eb..4b87899 100644 --- a/test/MC/AsmParser/macro-args.s +++ b/test/MC/AsmParser/macro-args.s @@ -8,3 +8,13 @@ GET is_sse, %eax // CHECK: movl is_sse@GOTOFF(%ebx), %eax + +.macro bar + .long $n +.endm + +bar 1, 2, 3 +bar + +// CHECK: .long 3 +// CHECK: .long 0 diff --git a/test/MC/AsmParser/variables-invalid.s b/test/MC/AsmParser/variables-invalid.s index 21758d2..c466d42 100644 --- a/test/MC/AsmParser/variables-invalid.s +++ b/test/MC/AsmParser/variables-invalid.s @@ -13,6 +13,7 @@ t2_s0: t2_s0 = 2 t3_s0 = t2_s0 + 1 + .long t3_s0 // CHECK: invalid reassignment of non-absolute variable 't3_s0' t3_s0 = 1 diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index e4346ec..998e9e8 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -1869,3 +1869,195 @@ # CHECK: vmov.f32 d0, #1.600000e+01 # CHECK: vmov.f32 q0, #1.600000e+01 +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16] + +# rdar://11034702 +0x0d 0x87 0x04 0xf4 +# CHECK: vst1.8 {d8}, [r4]! +0x4d 0x87 0x04 0xf4 +# CHECK: vst1.16 {d8}, [r4]! +0x8d 0x87 0x04 0xf4 +# CHECK: vst1.32 {d8}, [r4]! +0xcd 0x87 0x04 0xf4 +# CHECK: vst1.64 {d8}, [r4]! +0x06 0x87 0x04 0xf4 +# CHECK: vst1.8 {d8}, [r4], r6 +0x46 0x87 0x04 0xf4 +# CHECK: vst1.16 {d8}, [r4], r6 +0x86 0x87 0x04 0xf4 +# CHECK: vst1.32 {d8}, [r4], r6 +0xc6 0x87 0x04 0xf4 +# CHECK: vst1.64 {d8}, [r4], r6 + +0x0d 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4]! +0x4d 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4]! +0x8d 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4]! +0xcd 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4]! +0x06 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4], r6 +0x46 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4], r6 +0x86 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4], r6 +0xc6 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4], r6 + +0x0d 0x86 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10}, [r4]! +0x4d 0x86 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10}, [r4]! +0x8d 0x86 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10}, [r4]! +0xcd 0x86 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10}, [r4]! +0x06 0x86 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10}, [r4], r6 +0x46 0x86 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10}, [r4], r6 +0x86 0x86 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10}, [r4], r6 +0xc6 0x86 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10}, [r4], r6 + +0x0d 0x82 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x82 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x82 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4]! +0xcd 0x82 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4]! +0x06 0x82 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4], r6 +0x46 0x82 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4], r6 +0x86 0x82 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4], r6 +0xc6 0x82 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4], r6 + +0x0d 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x4d 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x8d 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x06 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4], r6 +0x46 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x86 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4], r6 + +0x0d 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4]! +0x4d 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4]! +0x8d 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4]! +0x06 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4], r6 +0x46 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4], r6 +0x86 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4], r6 + +0x0d 0x84 0x04 0xf4 +# CHECK: vst3.8 {d8, d9, d10}, [r4]! +0x4d 0x84 0x04 0xf4 +# CHECK: vst3.16 {d8, d9, d10}, [r4]! +0x8d 0x84 0x04 0xf4 +# CHECK: vst3.32 {d8, d9, d10}, [r4]! +0x06 0x85 0x04 0xf4 +# CHECK: vst3.8 {d8, d10, d12}, [r4], r6 +0x46 0x85 0x04 0xf4 +# CHECK: vst3.16 {d8, d10, d12}, [r4], r6 +0x86 0x85 0x04 0xf4 +# CHECK: vst3.32 {d8, d10, d12}, [r4], r6 + +0x0d 0x80 0x04 0xf4 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x80 0x04 0xf4 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x80 0x04 0xf4 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4]! +0x06 0x81 0x04 0xf4 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4], r6 +0x46 0x81 0x04 0xf4 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4], r6 +0x86 0x81 0x04 0xf4 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4], r6 + +0x4f 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4] +0x8f 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4] +0xcf 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4] +0x0f 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4] + +0x4f 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4] +0x8f 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4] +0x0f 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4] + +0x4d 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x46 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x8d 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x86 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4], r6 +0x0d 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x06 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4], r6 + +0x4f 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4] +0x8f 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4] +0x0f 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4] + +0x0f 0x84 0x04 0xf4 +# CHECK: vst3.8 {d8, d9, d10}, [r4] +0x4f 0x84 0x04 0xf4 +# CHECK: vst3.16 {d8, d9, d10}, [r4] +0x8f 0x84 0x04 0xf4 +# CHECK: vst3.32 {d8, d9, d10}, [r4] + +0x0f 0x80 0x04 0xf4 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4] +0x4f 0x80 0x04 0xf4 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4] +0x8f 0x80 0x04 0xf4 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4] + +0x0f 0x85 0x04 0xf4 +# CHECK: vst3.8 {d8, d10, d12}, [r4] +0x4f 0x85 0x04 0xf4 +# CHECK: vst3.16 {d8, d10, d12}, [r4] +0x8f 0x85 0x04 0xf4 +# CHECK: vst3.32 {d8, d10, d12}, [r4] + +0x0f 0x81 0x04 0xf4 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4] +0x4f 0x81 0x04 0xf4 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4] +0x8f 0x81 0x04 0xf4 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4] diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index ff1838e..f8e7dbe 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1588,3 +1588,193 @@ 0x63 0xf9 0x37 0xc9 # CHECK: vld2.8 {d28, d30}, [r3, :256], r7 +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16] + +# rdar://11034702 +0x04 0xf9 0x0d 0x87 +# CHECK: vst1.8 {d8}, [r4]! +0x04 0xf9 0x4d 0x87 +# CHECK: vst1.16 {d8}, [r4]! +0x04 0xf9 0x8d 0x87 +# CHECK: vst1.32 {d8}, [r4]! +0x04 0xf9 0xcd 0x87 +# CHECK: vst1.64 {d8}, [r4]! +0x04 0xf9 0x06 0x87 +# CHECK: vst1.8 {d8}, [r4], r6 +0x04 0xf9 0x46 0x87 +# CHECK: vst1.16 {d8}, [r4], r6 +0x04 0xf9 0x86 0x87 +# CHECK: vst1.32 {d8}, [r4], r6 +0x04 0xf9 0xc6 0x87 +# CHECK: vst1.64 {d8}, [r4], r6 + +0x04 0xf9 0x0d 0x8a +# CHECK: vst1.8 {d8, d9}, [r4]! +0x04 0xf9 0x4d 0x8a +# CHECK: vst1.16 {d8, d9}, [r4]! +0x04 0xf9 0x8d 0x8a +# CHECK: vst1.32 {d8, d9}, [r4]! +0x04 0xf9 0xcd 0x8a +# CHECK: vst1.64 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x8a +# CHECK: vst1.8 {d8, d9}, [r4], r6 +0x04 0xf9 0x46 0x8a +# CHECK: vst1.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x86 0x8a +# CHECK: vst1.32 {d8, d9}, [r4], r6 +0x04 0xf9 0xc6 0x8a +# CHECK: vst1.64 {d8, d9}, [r4], r6 + +0x04 0xf9 0x0d 0x86 +# CHECK: vst1.8 {d8, d9, d10}, [r4]! +0x04 0xf9 0x4d 0x86 +# CHECK: vst1.16 {d8, d9, d10}, [r4]! +0x04 0xf9 0x8d 0x86 +# CHECK: vst1.32 {d8, d9, d10}, [r4]! +0x04 0xf9 0xcd 0x86 +# CHECK: vst1.64 {d8, d9, d10}, [r4]! +0x04 0xf9 0x06 0x86 +# CHECK: vst1.8 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0x46 0x86 +# CHECK: vst1.16 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0x86 0x86 +# CHECK: vst1.32 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0xc6 0x86 +# CHECK: vst1.64 {d8, d9, d10}, [r4], r6 + +0x04 0xf9 0x0d 0x82 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x4d 0x82 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x8d 0x82 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0xcd 0x82 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x06 0x82 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0x46 0x82 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0x86 0x82 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0xc6 0x82 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4], r6 + +0x04 0xf9 0x0d 0x88 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x04 0xf9 0x4d 0x88 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x04 0xf9 0x8d 0x88 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x88 +# CHECK: vst2.8 {d8, d9}, [r4], r6 +0x04 0xf9 0x46 0x88 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x86 0x88 +# CHECK: vst2.32 {d8, d9}, [r4], r6 + +0x04 0xf9 0x0d 0x89 +# CHECK: vst2.8 {d8, d10}, [r4]! +0x04 0xf9 0x4d 0x89 +# CHECK: vst2.16 {d8, d10}, [r4]! +0x04 0xf9 0x8d 0x89 +# CHECK: vst2.32 {d8, d10}, [r4]! +0x04 0xf9 0x06 0x89 +# CHECK: vst2.8 {d8, d10}, [r4], r6 +0x04 0xf9 0x46 0x89 +# CHECK: vst2.16 {d8, d10}, [r4], r6 +0x04 0xf9 0x86 0x89 +# CHECK: vst2.32 {d8, d10}, [r4], r6 + +0x04 0xf9 0x0d 0x84 +# CHECK: vst3.8 {d8, d9, d10}, [r4]! +0x04 0xf9 0x4d 0x84 +# CHECK: vst3.16 {d8, d9, d10}, [r4]! +0x04 0xf9 0x8d 0x84 +# CHECK: vst3.32 {d8, d9, d10}, [r4]! +0x04 0xf9 0x06 0x85 +# CHECK: vst3.8 {d8, d10, d12}, [r4], r6 +0x04 0xf9 0x46 0x85 +# CHECK: vst3.16 {d8, d10, d12}, [r4], r6 +0x04 0xf9 0x86 0x85 +# CHECK: vst3.32 {d8, d10, d12}, [r4], r6 + +0x04 0xf9 0x0d 0x80 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x4d 0x80 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x8d 0x80 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x06 0x81 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4], r6 +0x04 0xf9 0x46 0x81 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4], r6 +0x04 0xf9 0x86 0x81 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4], r6 + +0x04 0xf9 0x4f 0x8a +# CHECK: vst1.16 {d8, d9}, [r4] +0x04 0xf9 0x8f 0x8a +# CHECK: vst1.32 {d8, d9}, [r4] +0x04 0xf9 0xcf 0x8a +# CHECK: vst1.64 {d8, d9}, [r4] +0x04 0xf9 0x0f 0x8a +# CHECK: vst1.8 {d8, d9}, [r4] +0x04 0xf9 0x4f 0x88 +# CHECK: vst2.16 {d8, d9}, [r4] +0x04 0xf9 0x8f 0x88 +# CHECK: vst2.32 {d8, d9}, [r4] +0x04 0xf9 0x0f 0x88 +# CHECK: vst2.8 {d8, d9}, [r4] +0x04 0xf9 0x4d 0x88 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x04 0xf9 0x46 0x88 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x8d 0x88 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x04 0xf9 0x86 0x88 +# CHECK: vst2.32 {d8, d9}, [r4], r6 +0x04 0xf9 0x0d 0x88 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x88 +# CHECK: vst2.8 {d8, d9}, [r4], r6 + +0x04 0xf9 0x4f 0x89 +# CHECK: vst2.16 {d8, d10}, [r4] +0x04 0xf9 0x8f 0x89 +# CHECK: vst2.32 {d8, d10}, [r4] +0x04 0xf9 0x0f 0x89 +# CHECK: vst2.8 {d8, d10}, [r4] + +0x04 0xf9 0x0f 0x84 +# CHECK: vst3.8 {d8, d9, d10}, [r4] +0x04 0xf9 0x4f 0x84 +# CHECK: vst3.16 {d8, d9, d10}, [r4] +0x04 0xf9 0x8f 0x84 +# CHECK: vst3.32 {d8, d9, d10}, [r4] + +0x04 0xf9 0x0f 0x80 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4] +0x04 0xf9 0x4f 0x80 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4] +0x04 0xf9 0x8f 0x80 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4] + +0x04 0xf9 0x0f 0x85 +# CHECK: vst3.8 {d8, d10, d12}, [r4] +0x04 0xf9 0x4f 0x85 +# CHECK: vst3.16 {d8, d10, d12}, [r4] +0x04 0xf9 0x8f 0x85 +# CHECK: vst3.32 {d8, d10, d12}, [r4] + +0x04 0xf9 0x0f 0x81 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4] +0x04 0xf9 0x4f 0x81 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4] +0x04 0xf9 0x8f 0x81 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4] diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt index 6a1f11f..f7d6bc6 100644 --- a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.89 LSL (register) # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x12 0xf1 0xa0 0xe1 diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt index 096b909..5b13610 100644 --- a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -6,4 +6,6 @@ # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x5f 0xf8 0xe4 0x30 diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt index b236f8e..874378e 100644 --- a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.183 SSAT # if d == 15 || n == 15 then UNPREDICTABLE; + +# CHECK:warning: potentially undefined instruction encoding 0x1a 0xf4 0xa0 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt index d3998bd..fef6125 100644 --- a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -7,4 +7,6 @@ # ------------------------------------------------------------------------------------------------- # # if t == 15 then UNPREDICTABLE + +# CHECK: warning: potentially undefined instruction encoding 0x00 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt index fb3e711..4c4c9ab 100644 --- a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -10,3 +10,7 @@ # # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; 0x9f 0x5f 0x66 0xe6 + +# CHECK: warning: potentially undefined +# CHECK: uqadd8 r5, r6, pc + diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index 54b242d..e2883c7 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -77,3 +77,25 @@ # CHECK: test RAX, 0 0x48 0xa9 0x00 0x00 0x00 0x00 + +# CHECK: sysret +0x48 0x0f 0x07 + +# CHECK: sysret +0x0f 0x07 + +# CHECK: sysexit +0x48 0x0f 0x35 + +# CHECK: sysexit +0x0f 0x35 + +# CHECK: iret +0x66 0xcf + +# CHECK: iretd +0xcf + +# CHECK: iretq +0x48 0xcf + diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 840d5fa..c0e77d0 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -724,3 +724,8 @@ # CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 0xc4 0xe3 0xe1 0x48 0x40 0x04 0x21 + +# rdar://8812056 lldb doesn't print the x86 lock prefix when disassembling +# CHECK: lock +# CHECK-NEXT: xaddq %rcx, %rbx +0xf0 0x48 0x0f 0xc1 0xcb diff --git a/test/MC/MachO/ARM/static-movt-relocs.s b/test/MC/MachO/ARM/static-movt-relocs.s new file mode 100644 index 0000000..dce5683 --- /dev/null +++ b/test/MC/MachO/ARM/static-movt-relocs.s @@ -0,0 +1,23 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s + .thumb + .thumb_func foo +foo: + movw r0, :lower16:(bar + 16) + movt r0, :upper16:(bar + 16) + bx r0 + + +@ CHECK: ('_relocations', [ +@ CHECK: # Relocation 0 +@ CHECK: (('word-0', 0x4), +@ CHECK: ('word-1', 0x8e000001)), +@ CHECK: # Relocation 1 +@ CHECK: (('word-0', 0x10), +@ CHECK: ('word-1', 0x16ffffff)), +@ CHECK: # Relocation 2 +@ CHECK: (('word-0', 0x0), +@ CHECK: ('word-1', 0x8c000001)), +@ CHECK: # Relocation 3 +@ CHECK: (('word-0', 0x0), +@ CHECK: ('word-1', 0x14ffffff)), +@ CHECK: ]) diff --git a/test/MC/Mips/elf-bigendian.ll b/test/MC/Mips/elf-bigendian.ll new file mode 100644 index 0000000..875ba3b --- /dev/null +++ b/test/MC/Mips/elf-bigendian.ll @@ -0,0 +1,45 @@ +; RUN: llc -filetype=obj -mtriple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check that this is big endian. +; CHECK: ('e_indent[EI_DATA]', 0x02) + +; Make sure that a section table (text) entry is correct. +; CHECK: (('sh_name', 0x{{[0]*}}5) # '.text' +; CHECKNEXT: ('sh_type', 0x{{[0]*}}1) +; CHECKNEXT: ('sh_flags', 0x{{[0]*}}6) +; CHECKNEXT: ('sh_addr', 0x{{{[0-9,a-f]+}}) +; CHECKNEXT: ('sh_offset', 0x{{{[0-9,a-f]+}}) +; CHECKNEXT: ('sh_size', 0x{{{[0-9,a-f]+}}) +; CHECKNEXT: ('sh_link', 0x{{[0]+}}) +; CHECKNEXT: ('sh_info', 0x{{[0]+}}) +; CHECKNEXT: ('sh_addralign', 0x{{[0]*}}4) +; CHECKNEXT: ('sh_entsize', 0x{{[0]+}}) + +; See that at least first 3 instructions are correct: GP prologue +; CHECKNEXT: ('_section_data', '3c1c0000 279c0000 0399e021 {{[0-9,a-f]*}}') + +; ModuleID = '../br1.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32" +target triple = "mips-unknown-linux" + +@x = global i32 1, align 4 +@str = private unnamed_addr constant [4 x i8] c"goo\00" +@str2 = private unnamed_addr constant [4 x i8] c"foo\00" + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.end, label %foo + +if.end: ; preds = %entry + %puts = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str, i32 0, i32 0)) + br label %foo + +foo: ; preds = %entry, %if.end + %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str2, i32 0, i32 0)) + ret i32 0 +} + +declare i32 @puts(i8* nocapture) nounwind + diff --git a/test/MC/Mips/elf_basic.s b/test/MC/Mips/elf_basic.s index 4621182..f7ed348 100644 --- a/test/MC/Mips/elf_basic.s +++ b/test/MC/Mips/elf_basic.s @@ -1,7 +1,7 @@ -; RUN: llc -filetype=obj -mtriple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE %s +// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE %s +// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE %s -; Check that we produce the correct endian. +// Check that we produce the correct endian. -; CHECK-BE: ('e_indent[EI_DATA]', 0x02) -; CHECK-LE: ('e_indent[EI_DATA]', 0x01) +// CHECK-BE: ('e_indent[EI_DATA]', 0x02) +// CHECK-LE: ('e_indent[EI_DATA]', 0x01) diff --git a/test/MC/X86/address-size.s b/test/MC/X86/address-size.s new file mode 100644 index 0000000..b105b40 --- /dev/null +++ b/test/MC/X86/address-size.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + + .code64 + movb $0x0, (%esi) +// CHECK: encoding: [0x67,0xc6,0x06,0x00] + movb $0x0, (%rsi) +// CHECK: encoding: [0xc6,0x06,0x00] + + .code32 + movb $0x0, (%si) +// CHECK: encoding: [0x67,0xc6,0x06,0x00] + movb $0x0, (%esi) +// CHECK: encoding: [0xc6,0x06,0x00] diff --git a/test/MC/X86/lit.local.cfg b/test/MC/X86/lit.local.cfg index 149a9a3..eee568e 100644 --- a/test/MC/X86/lit.local.cfg +++ b/test/MC/X86/lit.local.cfg @@ -1 +1,12 @@ config.suffixes = ['.ll', '.c', '.cpp', '.s'] + +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +targets = set(root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index d5e1b9c..f53b672 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -340,19 +340,27 @@ rclb $2, %bl // CHECK: rclb $2, %bl # encoding: [0xc0,0xd3,0x02] // rdar://8418316 // PR12173 -// CHECK: shldw %cl, %bx, %bx -// CHECK: shldw %cl, %bx, %bx -// CHECK: shldw $1, %bx, %bx -// CHECK: shrdw %cl, %bx, %bx -// CHECK: shrdw %cl, %bx, %bx -// CHECK: shrdw $1, %bx, %bx - -shld %bx, %bx -shld %cl, %bx, %bx -shld $1, %bx, %bx -shrd %bx, %bx -shrd %cl, %bx, %bx -shrd $1, %bx, %bx +// CHECK: shldw %cl, %bx, %dx +// CHECK: shldw %cl, %bx, %dx +// CHECK: shldw $1, %bx, %dx +// CHECK: shldw %cl, %bx, (%rax) +// CHECK: shldw %cl, %bx, (%rax) +// CHECK: shrdw %cl, %bx, %dx +// CHECK: shrdw %cl, %bx, %dx +// CHECK: shrdw $1, %bx, %dx +// CHECK: shrdw %cl, %bx, (%rax) +// CHECK: shrdw %cl, %bx, (%rax) + +shld %bx, %dx +shld %cl, %bx, %dx +shld $1, %bx, %dx +shld %bx, (%rax) +shld %cl, %bx, (%rax) +shrd %bx, %dx +shrd %cl, %bx, %dx +shrd $1, %bx, %dx +shrd %bx, (%rax) +shrd %cl, %bx, (%rax) // CHECK: sldtl %ecx // CHECK: encoding: [0x0f,0x00,0xc1] @@ -1045,6 +1053,9 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1] movsl movsl %ds:(%rsi), %es:(%rdi) movsl (%rsi), %es:(%rdi) +// rdar://10883092 +// CHECK: movsd + movsl (%rsi), (%rdi) // CHECK: movsq # encoding: [0x48,0xa5] // CHECK: movsq diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s index 8de7444..f161e06 100644 --- a/test/MC/X86/x86_errors.s +++ b/test/MC/X86/x86_errors.s @@ -20,3 +20,11 @@ movl 0(%rax), 0(%edx) // error: invalid operand for instruction // 32: error: instruction requires a CPU feature not currently enabled sysexitq + +// rdar://10710167 +// 64: error: expected scale expression +lea (%rsp, %rbp, $4), %rax + +// rdar://10423777 +// 64: error: index register is 32-bit, but base register is 64-bit +movq (%rsi,%ecx),%xmm0 diff --git a/test/Makefile b/test/Makefile index a4e53f8..6cd27cc 100644 --- a/test/Makefile +++ b/test/Makefile @@ -171,6 +171,7 @@ lit.site.cfg: site.exp @$(ECHOPATH) s=@ENABLE_ASSERTIONS@=$(ENABLE_ASSERTIONS)=g >> lit.tmp @$(ECHOPATH) s=@TARGETS_TO_BUILD@=$(TARGETS_TO_BUILD)=g >> lit.tmp @$(ECHOPATH) s=@LLVM_BINDINGS@=$(BINDINGS_TO_BUILD)=g >> lit.tmp + @$(ECHOPATH) s=@HOST_OS@=$(HOST_OS)=g >> lit.tmp @sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@ @-rm -f lit.tmp @@ -184,5 +185,6 @@ Unit/lit.site.cfg: $(PROJ_OBJ_DIR)/Unit/.dir FORCE @$(ECHOPATH) s=@ENABLE_SHARED@=$(ENABLE_SHARED)=g >> unit.tmp @$(ECHOPATH) s=@SHLIBDIR@=$(SharedLibDir)=g >> unit.tmp @$(ECHOPATH) s=@SHLIBPATH_VAR@=$(SHLIBPATH_VAR)=g >> unit.tmp + @$(ECHOPATH) s=@HOST_OS@=$(HOST_OS)=g >> unit.tmp @sed -f unit.tmp $(PROJ_SRC_DIR)/Unit/lit.site.cfg.in > $@ @-rm -f unit.tmp diff --git a/test/Object/Inputs/elf-versioning-test.i386 b/test/Object/Inputs/elf-versioning-test.i386 Binary files differnew file mode 100755 index 0000000..c7c1eac --- /dev/null +++ b/test/Object/Inputs/elf-versioning-test.i386 diff --git a/test/Object/Inputs/elf-versioning-test.x86_64 b/test/Object/Inputs/elf-versioning-test.x86_64 Binary files differnew file mode 100755 index 0000000..cba79ba --- /dev/null +++ b/test/Object/Inputs/elf-versioning-test.x86_64 diff --git a/test/Object/Inputs/elfver.S b/test/Object/Inputs/elfver.S new file mode 100644 index 0000000..ba63279 --- /dev/null +++ b/test/Object/Inputs/elfver.S @@ -0,0 +1,31 @@ +# Compile with: +# ARGS="-shared -nostdlib -Wl,--version-script=elfver.script" +# clang $ARGS -m32 elfver.S -lc -o elf-versioning-test.i386 +# clang $ARGS -m64 elfver.S -lc -o elf-versioning-test.x86_64 + +# Also, strip off non-dynamic symbols: +# strip elf-versioning-test.i386 +# strip elf-versioning-test.x86_64 + +#ifdef __i386__ +.symver _puts, puts@GLIBC_2.0 +#else +.symver _puts, puts@GLIBC_2.2.5 +#endif +call _puts@PLT + +.symver foo1, foo@VER1 +.globl foo1 +.type foo1, @function +foo1: + ret + +.symver foo2, foo@@VER2 +.globl foo2 +.type foo2, @function +foo2: + ret + +.globl unversioned_define +.type unversioned_define, @function +unversioned_define: diff --git a/test/Object/Inputs/elfver.script b/test/Object/Inputs/elfver.script new file mode 100644 index 0000000..1316fcb --- /dev/null +++ b/test/Object/Inputs/elfver.script @@ -0,0 +1,10 @@ +VER1 { + global: + foo; +}; + +VER2 { + global: + foo; +} VER1; + diff --git a/test/Object/readobj-elf-versioning.test b/test/Object/readobj-elf-versioning.test new file mode 100644 index 0000000..0906f34 --- /dev/null +++ b/test/Object/readobj-elf-versioning.test @@ -0,0 +1,15 @@ +RUN: llvm-readobj %p/Inputs/elf-versioning-test.i386 \ +RUN: | FileCheck %s -check-prefix ELF +RUN: llvm-readobj %p/Inputs/elf-versioning-test.i386 \ +RUN: | FileCheck %s -check-prefix ELF32 +RUN: llvm-readobj %p/Inputs/elf-versioning-test.x86_64 \ +RUN: | FileCheck %s -check-prefix ELF +RUN: llvm-readobj %p/Inputs/elf-versioning-test.x86_64 \ +RUN: | FileCheck %s -check-prefix ELF64 + +ELF: foo@@VER2 FUNC {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} global +ELF: foo@VER1 FUNC {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} global +ELF: unversioned_define FUNC {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} global + +ELF32: puts@GLIBC_2.0 FUNC {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} undef,global +ELF64: puts@GLIBC_2.2.5 FUNC {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} undef,global diff --git a/test/TableGen/TwoLevelName.td b/test/TableGen/TwoLevelName.td new file mode 100644 index 0000000..9c502f4 --- /dev/null +++ b/test/TableGen/TwoLevelName.td @@ -0,0 +1,46 @@ +// RUN: llvm-tblgen %s | FileCheck %s +// XFAIL: vg_leak + +class Type<string name, int length, int width> { + string Name = name; + int Length = length; + int Width = width; +} + +multiclass OT1<string ss, int l, int w> { + def _#NAME# : Type<ss, l, w>; +} +multiclass OT2<string ss, int w> { + defm v1#NAME# : OT1<!strconcat( "v1", ss), 1, w>; + defm v2#NAME# : OT1<!strconcat( "v2", ss), 2, w>; + defm v3#NAME# : OT1<!strconcat( "v3", ss), 3, w>; + defm v4#NAME# : OT1<!strconcat( "v4", ss), 4, w>; + defm v8#NAME# : OT1<!strconcat( "v8", ss), 8, w>; + defm v16#NAME# : OT1<!strconcat("v16", ss), 16, w>; +} + +defm i8 : OT2<"i8", 8>; + +// CHECK: _v16i8 +// CHECK: Length = 16 +// CHECK: Width = 8 + +// CHECK: _v1i8 +// CHECK: Length = 1 +// CHECK: Width = 8 + +// CHECK: _v2i8 +// CHECK: Length = 2 +// CHECK: Width = 8 + +// CHECK: _v3i8 +// CHECK: Length = 3 +// CHECK: Width = 8 + +// CHECK: _v4i8 +// CHECK: Length = 4 +// CHECK: Width = 8 + +// CHECK: _v8i8 +// CHECK: Length = 8 +// CHECK: Width = 8 diff --git a/test/Transforms/CorrelatedValuePropagation/basic.ll b/test/Transforms/CorrelatedValuePropagation/basic.ll index 270c048..475cd8d 100644 --- a/test/Transforms/CorrelatedValuePropagation/basic.ll +++ b/test/Transforms/CorrelatedValuePropagation/basic.ll @@ -79,4 +79,103 @@ Impossible: LessThanOrEqualToTwo: ret i32 0 -}
\ No newline at end of file +} + +define i32 @switch1(i32 %s) { +; CHECK: @switch1 +entry: + %cmp = icmp slt i32 %s, 0 + br i1 %cmp, label %negative, label %out + +negative: + switch i32 %s, label %out [ +; CHECK: switch i32 %s, label %out + i32 0, label %out +; CHECK-NOT: i32 0 + i32 1, label %out +; CHECK-NOT: i32 1 + i32 -1, label %next +; CHECK: i32 -1, label %next + i32 -2, label %next +; CHECK: i32 -2, label %next + i32 2, label %out +; CHECK-NOT: i32 2 + i32 3, label %out +; CHECK-NOT: i32 3 + ] + +out: + %p = phi i32 [ 1, %entry ], [ -1, %negative ], [ -1, %negative ], [ -1, %negative ], [ -1, %negative ] + ret i32 %p + +next: + %q = phi i32 [ 0, %negative ], [ 0, %negative ] + ret i32 %q +} + +define i32 @switch2(i32 %s) { +; CHECK: @switch2 +entry: + %cmp = icmp sgt i32 %s, 0 + br i1 %cmp, label %positive, label %out + +positive: + switch i32 %s, label %out [ + i32 0, label %out + i32 -1, label %next + i32 -2, label %next + ] +; CHECK: br label %out + +out: + %p = phi i32 [ -1, %entry ], [ 1, %positive ], [ 1, %positive ] + ret i32 %p + +next: + %q = phi i32 [ 0, %positive ], [ 0, %positive ] + ret i32 %q +} + +define i32 @switch3(i32 %s) { +; CHECK: @switch3 +entry: + %cmp = icmp sgt i32 %s, 0 + br i1 %cmp, label %positive, label %out + +positive: + switch i32 %s, label %out [ + i32 -1, label %out + i32 -2, label %next + i32 -3, label %next + ] +; CHECK: br label %out + +out: + %p = phi i32 [ -1, %entry ], [ 1, %positive ], [ 1, %positive ] + ret i32 %p + +next: + %q = phi i32 [ 0, %positive ], [ 0, %positive ] + ret i32 %q +} + +define void @switch4(i32 %s) { +; CHECK: @switch4 +entry: + %cmp = icmp eq i32 %s, 0 + br i1 %cmp, label %zero, label %out + +zero: + switch i32 %s, label %out [ + i32 0, label %next + i32 1, label %out + i32 -1, label %out + ] +; CHECK: br label %next + +out: + ret void + +next: + ret void +} diff --git a/test/Transforms/EarlyCSE/instsimplify-dom.ll b/test/Transforms/EarlyCSE/instsimplify-dom.ll new file mode 100644 index 0000000..36dffec --- /dev/null +++ b/test/Transforms/EarlyCSE/instsimplify-dom.ll @@ -0,0 +1,19 @@ +; RUN: opt -early-cse -S < %s | FileCheck %s +; PR12231 + +declare i32 @f() + +define i32 @fn() { +entry: + br label %lbl_1215 + +lbl_1215: + %ins34 = phi i32 [ %ins35, %xxx ], [ undef, %entry ] + ret i32 %ins34 + +xxx: + %ins35 = call i32 @f() + br label %lbl_1215 +} + +; CHECK: define i32 @fn diff --git a/test/Transforms/GlobalOpt/invoke.ll b/test/Transforms/GlobalOpt/invoke.ll new file mode 100644 index 0000000..c1f499c --- /dev/null +++ b/test/Transforms/GlobalOpt/invoke.ll @@ -0,0 +1,27 @@ +; RUN: opt -S -globalopt < %s | FileCheck %s +; rdar://11022897 + +; Globalopt should be able to evaluate an invoke. +; CHECK: @tmp = global i32 1 + +@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }] +@tmp = global i32 0 + +define i32 @one() { + ret i32 1 +} + +define void @_GLOBAL__I_a() { +bb: + %tmp1 = invoke i32 @one() + to label %bb2 unwind label %bb4 + +bb2: ; preds = %bb + store i32 %tmp1, i32* @tmp + ret void + +bb4: ; preds = %bb + %tmp5 = landingpad { i8*, i32 } personality i8* undef + filter [0 x i8*] zeroinitializer + unreachable +} diff --git a/test/Transforms/Inline/2007-06-06-NoInline.ll b/test/Transforms/Inline/2007-06-06-NoInline.ll deleted file mode 100644 index d5a7953..0000000 --- a/test/Transforms/Inline/2007-06-06-NoInline.ll +++ /dev/null @@ -1,46 +0,0 @@ -; RUN: opt < %s -inline -S | grep "define internal i32 @bar" -@llvm.noinline = appending global [1 x i8*] [ i8* bitcast (i32 (i32, i32)* @bar to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define internal i32 @bar(i32 %x, i32 %y) { -entry: - %x_addr = alloca i32 ; <i32*> [#uses=2] - %y_addr = alloca i32 ; <i32*> [#uses=2] - %retval = alloca i32, align 4 ; <i32*> [#uses=2] - %tmp = alloca i32, align 4 ; <i32*> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i32 %x, i32* %x_addr - store i32 %y, i32* %y_addr - %tmp1 = load i32* %x_addr ; <i32> [#uses=1] - %tmp2 = load i32* %y_addr ; <i32> [#uses=1] - %tmp3 = add i32 %tmp1, %tmp2 ; <i32> [#uses=1] - store i32 %tmp3, i32* %tmp - %tmp4 = load i32* %tmp ; <i32> [#uses=1] - store i32 %tmp4, i32* %retval - br label %return - -return: ; preds = %entry - %retval5 = load i32* %retval ; <i32> [#uses=1] - ret i32 %retval5 -} - -define i32 @foo(i32 %a, i32 %b) { -entry: - %a_addr = alloca i32 ; <i32*> [#uses=2] - %b_addr = alloca i32 ; <i32*> [#uses=2] - %retval = alloca i32, align 4 ; <i32*> [#uses=2] - %tmp = alloca i32, align 4 ; <i32*> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i32 %a, i32* %a_addr - store i32 %b, i32* %b_addr - %tmp1 = load i32* %b_addr ; <i32> [#uses=1] - %tmp2 = load i32* %a_addr ; <i32> [#uses=1] - %tmp3 = call i32 @bar( i32 %tmp1, i32 %tmp2 ) ; <i32> [#uses=1] - store i32 %tmp3, i32* %tmp - %tmp4 = load i32* %tmp ; <i32> [#uses=1] - store i32 %tmp4, i32* %retval - br label %return - -return: ; preds = %entry - %retval5 = load i32* %retval ; <i32> [#uses=1] - ret i32 %retval5 -} diff --git a/test/Transforms/Inline/alloca-bonus.ll b/test/Transforms/Inline/alloca-bonus.ll index 91ab40a..fb4062f 100644 --- a/test/Transforms/Inline/alloca-bonus.ll +++ b/test/Transforms/Inline/alloca-bonus.ll @@ -81,3 +81,44 @@ bb.true: bb.false: ret void } + +define void @outer4(i32 %A) { +; CHECK: @outer4 +; CHECK-NOT: call void @inner4 + %ptr = alloca i32 + call void @inner4(i32* %ptr, i32 %A) + ret void +} + +; %D poisons this call, scalar-repl can't handle that instruction. However, we +; still want to detect that the icmp and branch *can* be handled. +define void @inner4(i32 *%ptr, i32 %A) { + %B = getelementptr i32* %ptr, i32 %A + %E = icmp eq i32* %ptr, null + br i1 %E, label %bb.true, label %bb.false +bb.true: + ; This block musn't be counted in the inline cost. + %t1 = load i32* %ptr + %t2 = add i32 %t1, 1 + %t3 = add i32 %t2, 1 + %t4 = add i32 %t3, 1 + %t5 = add i32 %t4, 1 + %t6 = add i32 %t5, 1 + %t7 = add i32 %t6, 1 + %t8 = add i32 %t7, 1 + %t9 = add i32 %t8, 1 + %t10 = add i32 %t9, 1 + %t11 = add i32 %t10, 1 + %t12 = add i32 %t11, 1 + %t13 = add i32 %t12, 1 + %t14 = add i32 %t13, 1 + %t15 = add i32 %t14, 1 + %t16 = add i32 %t15, 1 + %t17 = add i32 %t16, 1 + %t18 = add i32 %t17, 1 + %t19 = add i32 %t18, 1 + %t20 = add i32 %t19, 1 + ret void +bb.false: + ret void +} diff --git a/test/Transforms/Inline/inline_constprop.ll b/test/Transforms/Inline/inline_constprop.ll index 537c69b..cc7aaac 100644 --- a/test/Transforms/Inline/inline_constprop.ll +++ b/test/Transforms/Inline/inline_constprop.ll @@ -1,14 +1,89 @@ -; RUN: opt < %s -inline -S | not grep callee -; RUN: opt < %s -inline -S | not grep div +; RUN: opt < %s -inline -S | FileCheck %s +define internal i32 @callee1(i32 %A, i32 %B) { + %C = sdiv i32 %A, %B + ret i32 %C +} + +define i32 @caller1() { +; CHECK: define i32 @caller1 +; CHECK-NEXT: ret i32 3 -define internal i32 @callee(i32 %A, i32 %B) { - %C = sdiv i32 %A, %B ; <i32> [#uses=1] - ret i32 %C + %X = call i32 @callee1( i32 10, i32 3 ) + ret i32 %X } -define i32 @test() { - %X = call i32 @callee( i32 10, i32 3 ) ; <i32> [#uses=1] - ret i32 %X +define i32 @caller2() { +; CHECK: @caller2 +; CHECK-NOT: call void @callee2 +; CHECK: ret + +; We contrive to make this hard for *just* the inline pass to do in order to +; simulate what can actually happen with large, complex functions getting +; inlined. + %a = add i32 42, 0 + %b = add i32 48, 0 + + %x = call i32 @callee21(i32 %a, i32 %b) + ret i32 %x } +define i32 @callee21(i32 %x, i32 %y) { + %sub = sub i32 %y, %x + %result = call i32 @callee22(i32 %sub) + ret i32 %result +} + +declare i8* @getptr() + +define i32 @callee22(i32 %x) { + %icmp = icmp ugt i32 %x, 42 + br i1 %icmp, label %bb.true, label %bb.false +bb.true: + ; This block musn't be counted in the inline cost. + %ptr = call i8* @getptr() + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + load volatile i8* %ptr + + ret i32 %x +bb.false: + ret i32 %x +} diff --git a/test/Transforms/Inline/ptr-diff.ll b/test/Transforms/Inline/ptr-diff.ll new file mode 100644 index 0000000..0b431d6 --- /dev/null +++ b/test/Transforms/Inline/ptr-diff.ll @@ -0,0 +1,56 @@ +; RUN: opt -inline < %s -S -o - -inline-threshold=10 | FileCheck %s + +define i32 @outer1() { +; CHECK: @outer1 +; CHECK-NOT: call +; CHECK: ret i32 + + %ptr = alloca i32 + %ptr1 = getelementptr inbounds i32* %ptr, i32 0 + %ptr2 = getelementptr inbounds i32* %ptr, i32 42 + %result = call i32 @inner1(i32* %ptr1, i32* %ptr2) + ret i32 %result +} + +define i32 @inner1(i32* %begin, i32* %end) { + %begin.i = ptrtoint i32* %begin to i32 + %end.i = ptrtoint i32* %end to i32 + %distance = sub i32 %end.i, %begin.i + %icmp = icmp sle i32 %distance, 42 + br i1 %icmp, label %then, label %else + +then: + ret i32 3 + +else: + %t = load i32* %begin + ret i32 %t +} + +define i32 @outer2(i32* %ptr) { +; Test that an inbounds GEP disables this -- it isn't safe in general as +; wrapping changes the behavior of lessthan and greaterthan comparisions. +; CHECK: @outer2 +; CHECK: call i32 @inner2 +; CHECK: ret i32 + + %ptr1 = getelementptr i32* %ptr, i32 0 + %ptr2 = getelementptr i32* %ptr, i32 42 + %result = call i32 @inner2(i32* %ptr1, i32* %ptr2) + ret i32 %result +} + +define i32 @inner2(i32* %begin, i32* %end) { + %begin.i = ptrtoint i32* %begin to i32 + %end.i = ptrtoint i32* %end to i32 + %distance = sub i32 %end.i, %begin.i + %icmp = icmp sle i32 %distance, 42 + br i1 %icmp, label %then, label %else + +then: + ret i32 3 + +else: + %t = load i32* %begin + ret i32 %t +} diff --git a/test/Transforms/InstCombine/2012-03-10-InstCombine.ll b/test/Transforms/InstCombine/2012-03-10-InstCombine.ll new file mode 100644 index 0000000..58ccf12 --- /dev/null +++ b/test/Transforms/InstCombine/2012-03-10-InstCombine.ll @@ -0,0 +1,35 @@ +; RUN: opt < %s -S -instcombine | FileCheck %s + +; Derived from gcc.c-torture/execute/frame-address.c + +; CHECK: @func +; CHECK: return: +; CHECK-NOT: ret i32 0 +; CHECK: ret i32 %retval + +define i32 @func(i8* %c, i8* %f) nounwind uwtable readnone noinline ssp { +entry: + %d = alloca i8, align 1 + store i8 0, i8* %d, align 1 + %cmp = icmp ugt i8* %d, %c + br i1 %cmp, label %if.else, label %if.then + +if.then: ; preds = %entry + %cmp2 = icmp ule i8* %d, %f + %not.cmp1 = icmp uge i8* %c, %f + %.cmp2 = and i1 %cmp2, %not.cmp1 + %land.ext = zext i1 %.cmp2 to i32 + br label %return + +if.else: ; preds = %entry + %cmp5 = icmp uge i8* %d, %f + %not.cmp3 = icmp ule i8* %c, %f + %.cmp5 = and i1 %cmp5, %not.cmp3 + %land.ext7 = zext i1 %.cmp5 to i32 + br label %return + +return: ; preds = %if.else, %if.then + %retval.0 = phi i32 [ %land.ext, %if.then ], [ %land.ext7, %if.else ] + ret i32 %retval.0 +} + diff --git a/test/Transforms/InstCombine/2012-3-15-or-xor-constant.ll b/test/Transforms/InstCombine/2012-3-15-or-xor-constant.ll new file mode 100644 index 0000000..c1602da --- /dev/null +++ b/test/Transforms/InstCombine/2012-3-15-or-xor-constant.ll @@ -0,0 +1,12 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +; PR12234 + +@g = extern_weak global i32 +define i32 @function(i32 %x) nounwind { +entry: + %xor = xor i32 %x, 1 + store volatile i32 %xor, i32* inttoptr (i64 1 to i32*), align 4 + %or4 = or i32 or (i32 zext (i1 icmp eq (i32* @g, i32* null) to i32), i32 1), %xor + ret i32 %or4 +} +; CHECK: define i32 @function diff --git a/test/Transforms/InstCombine/mul.ll b/test/Transforms/InstCombine/mul.ll index 53a5643..edb5305 100644 --- a/test/Transforms/InstCombine/mul.ll +++ b/test/Transforms/InstCombine/mul.ll @@ -1,116 +1,184 @@ ; This test makes sure that mul instructions are properly eliminated. -; RUN: opt < %s -instcombine -S | not grep mul +; RUN: opt < %s -instcombine -S | FileCheck %s define i32 @test1(i32 %A) { +; CHECK: @test1 %B = mul i32 %A, 1 ; <i32> [#uses=1] ret i32 %B +; CHECK: ret i32 %A } define i32 @test2(i32 %A) { +; CHECK: @test2 ; Should convert to an add instruction %B = mul i32 %A, 2 ; <i32> [#uses=1] ret i32 %B +; CHECK: shl i32 %A, 1 } define i32 @test3(i32 %A) { +; CHECK: @test3 ; This should disappear entirely %B = mul i32 %A, 0 ; <i32> [#uses=1] ret i32 %B +; CHECK: ret i32 0 } define double @test4(double %A) { +; CHECK: @test4 ; This is safe for FP %B = fmul double 1.000000e+00, %A ; <double> [#uses=1] ret double %B +; CHECK: ret double %A } define i32 @test5(i32 %A) { +; CHECK: @test5 %B = mul i32 %A, 8 ; <i32> [#uses=1] ret i32 %B +; CHECK: shl i32 %A, 3 } define i8 @test6(i8 %A) { +; CHECK: @test6 %B = mul i8 %A, 8 ; <i8> [#uses=1] %C = mul i8 %B, 8 ; <i8> [#uses=1] ret i8 %C +; CHECK: shl i8 %A, 6 } define i32 @test7(i32 %i) { +; CHECK: @test7 %tmp = mul i32 %i, -1 ; <i32> [#uses=1] ret i32 %tmp +; CHECK: sub i32 0, %i } define i64 @test8(i64 %i) { - ; tmp = sub 0, %i +; CHECK: @test8 %j = mul i64 %i, -1 ; <i64> [#uses=1] ret i64 %j +; CHECK: sub i64 0, %i } define i32 @test9(i32 %i) { - ; %j = sub 0, %i +; CHECK: @test9 %j = mul i32 %i, -1 ; <i32> [#uses=1] ret i32 %j +; CHECJ: sub i32 0, %i } define i32 @test10(i32 %a, i32 %b) { +; CHECK: @test10 %c = icmp slt i32 %a, 0 ; <i1> [#uses=1] %d = zext i1 %c to i32 ; <i32> [#uses=1] ; e = b & (a >> 31) %e = mul i32 %d, %b ; <i32> [#uses=1] ret i32 %e +; CHECK: [[TEST10:%.*]] = ashr i32 %a, 31 +; CHECK-NEXT: %e = and i32 [[TEST10]], %b +; CHECK-NEXT: ret i32 %e } define i32 @test11(i32 %a, i32 %b) { +; CHECK: @test11 %c = icmp sle i32 %a, -1 ; <i1> [#uses=1] %d = zext i1 %c to i32 ; <i32> [#uses=1] ; e = b & (a >> 31) %e = mul i32 %d, %b ; <i32> [#uses=1] ret i32 %e +; CHECK: [[TEST11:%.*]] = ashr i32 %a, 31 +; CHECK-NEXT: %e = and i32 [[TEST11]], %b +; CHECK-NEXT: ret i32 %e } -define i32 @test12(i8 %a, i32 %b) { - %c = icmp ugt i8 %a, 127 ; <i1> [#uses=1] +define i32 @test12(i32 %a, i32 %b) { +; CHECK: @test12 + %c = icmp ugt i32 %a, 2147483647 ; <i1> [#uses=1] %d = zext i1 %c to i32 ; <i32> [#uses=1] - ; e = b & (a >> 31) %e = mul i32 %d, %b ; <i32> [#uses=1] ret i32 %e +; CHECK: [[TEST12:%.*]] = ashr i32 %a, 31 +; CHECK-NEXT: %e = and i32 [[TEST12]], %b +; CHECK-NEXT: ret i32 %e + } ; PR2642 define internal void @test13(<4 x float>*) { +; CHECK: @test13 load <4 x float>* %0, align 1 fmul <4 x float> %2, < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 > store <4 x float> %3, <4 x float>* %0, align 1 ret void +; CHECK-NEXT: ret void } define <16 x i8> @test14(<16 x i8> %a) { +; CHECK: @test14 %b = mul <16 x i8> %a, zeroinitializer ret <16 x i8> %b +; CHECK-NEXT: ret <16 x i8> zeroinitializer } ; rdar://7293527 define i32 @test15(i32 %A, i32 %B) { +; CHECK: @test15 entry: %shl = shl i32 1, %B %m = mul i32 %shl, %A ret i32 %m +; CHECK: shl i32 %A, %B } ; X * Y (when Y is 0 or 1) --> x & (0-Y) define i32 @test16(i32 %b, i1 %c) { +; CHECK: @test16 %d = zext i1 %c to i32 ; <i32> [#uses=1] ; e = b & (a >> 31) %e = mul i32 %d, %b ; <i32> [#uses=1] ret i32 %e +; CHECK: [[TEST16:%.*]] = sext i1 %c to i32 +; CHECK-NEXT: %e = and i32 [[TEST16]], %b +; CHECK-NEXT: ret i32 %e } ; X * Y (when Y is 0 or 1) --> x & (0-Y) define i32 @test17(i32 %a, i32 %b) { +; CHECK: @test17 %a.lobit = lshr i32 %a, 31 %e = mul i32 %a.lobit, %b ret i32 %e +; CHECK: [[TEST17:%.*]] = ashr i32 %a, 31 +; CHECK-NEXT: %e = and i32 [[TEST17]], %b +; CHECK-NEXT: ret i32 %e +} + +define i32 @test18(i32 %A, i32 %B) { +; CHECK: @test18 + %C = and i32 %A, 1 + %D = and i32 %B, 1 + + %E = mul i32 %C, %D + %F = and i32 %E, 16 + ret i32 %F +; CHECK-NEXT: ret i32 0 } +declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) +declare void @use(i1) +define i32 @test19(i32 %A, i32 %B) { +; CHECK: @test19 + %C = and i32 %A, 1 + %D = and i32 %B, 1 +; It would be nice if we also started proving that this doesn't overflow. + %E = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %C, i32 %D) + %F = extractvalue {i32, i1} %E, 0 + %G = extractvalue {i32, i1} %E, 1 + call void @use(i1 %G) + %H = and i32 %F, 16 + ret i32 %H +; CHECK: ret i32 0 +} diff --git a/test/Transforms/InstSimplify/phi.ll b/test/Transforms/InstSimplify/phi.ll new file mode 100644 index 0000000..05cd40d --- /dev/null +++ b/test/Transforms/InstSimplify/phi.ll @@ -0,0 +1,22 @@ +; RUN: opt < %s -instsimplify -S | FileCheck %s + +; PR12189 +define i1 @test1(i32 %x) { +; CHECK: @test1 + br i1 true, label %a, label %b + +a: + %aa = or i32 %x, 10 + br label %c + +b: + %bb = or i32 %x, 10 + br label %c + +c: + %cc = phi i32 [ %bb, %b ], [%aa, %a ] + %d = urem i32 %cc, 2 + %e = icmp eq i32 %d, 0 + ret i1 %e +; CHECK: ret i1 %e +} diff --git a/test/Transforms/InstSimplify/ptr_diff.ll b/test/Transforms/InstSimplify/ptr_diff.ll new file mode 100644 index 0000000..013964c --- /dev/null +++ b/test/Transforms/InstSimplify/ptr_diff.ll @@ -0,0 +1,33 @@ +; RUN: opt < %s -instsimplify -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i64 @ptrdiff1(i8* %ptr) { +; CHECK: @ptrdiff1 +; CHECK-NEXT: ret i64 42 + + %first = getelementptr i8* %ptr, i32 0 + %last = getelementptr i8* %ptr, i32 42 + %first.int = ptrtoint i8* %first to i64 + %last.int = ptrtoint i8* %last to i64 + %diff = sub i64 %last.int, %first.int + ret i64 %diff +} + +define i64 @ptrdiff2(i8* %ptr) { +; CHECK: @ptrdiff2 +; CHECK-NEXT: ret i64 42 + + %first1 = getelementptr i8* %ptr, i32 0 + %first2 = getelementptr i8* %first1, i32 1 + %first3 = getelementptr i8* %first2, i32 2 + %first4 = getelementptr i8* %first3, i32 4 + %last1 = getelementptr i8* %first2, i32 48 + %last2 = getelementptr i8* %last1, i32 8 + %last3 = getelementptr i8* %last2, i32 -4 + %last4 = getelementptr i8* %last3, i32 -4 + %first.int = ptrtoint i8* %first4 to i64 + %last.int = ptrtoint i8* %last4 to i64 + %diff = sub i64 %last.int, %first.int + ret i64 %diff +} diff --git a/test/Transforms/InstSimplify/reassociate.ll b/test/Transforms/InstSimplify/reassociate.ll index 3c8169e..e659e6f 100644 --- a/test/Transforms/InstSimplify/reassociate.ll +++ b/test/Transforms/InstSimplify/reassociate.ll @@ -184,3 +184,12 @@ define i32 @udiv5(i32 %x, i32 %y) { ; CHECK: ret i32 %x } +define i16 @trunc1(i32 %x) { +; CHECK: @trunc1 + %y = add i32 %x, 1 + %tx = trunc i32 %x to i16 + %ty = trunc i32 %y to i16 + %d = sub i16 %ty, %tx + ret i16 %d +; CHECK: ret i16 1 +} diff --git a/test/Transforms/JumpThreading/thread-loads.ll b/test/Transforms/JumpThreading/thread-loads.ll index cce23ea..78d36e7 100644 --- a/test/Transforms/JumpThreading/thread-loads.ll +++ b/test/Transforms/JumpThreading/thread-loads.ll @@ -1,12 +1,12 @@ ; RUN: opt < %s -jump-threading -S | FileCheck %s -; rdar://6402033 -; Test that we can thread through the block with the partially redundant load (%2). target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin7" -define i32 @foo(i32* %P) nounwind { -; CHECK: foo +; Test that we can thread through the block with the partially redundant load (%2). +; rdar://6402033 +define i32 @test1(i32* %P) nounwind { +; CHECK: @test1 entry: %0 = tail call i32 (...)* @f1() nounwind ; <i32> [#uses=1] %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1] @@ -39,3 +39,43 @@ bb3: ; preds = %bb1 declare i32 @f1(...) declare i32 @f2(...) + + +;; Check that we preserve TBAA information. +; rdar://11039258 + +define i32 @test2(i32* %P) nounwind { +; CHECK: @test2 +entry: + %0 = tail call i32 (...)* @f1() nounwind ; <i32> [#uses=1] + %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1] + br i1 %1, label %bb1, label %bb + +bb: ; preds = %entry +; CHECK: bb1.thread: +; CHECK: store{{.*}}, !tbaa !0 +; CHECK: br label %bb3 + store i32 42, i32* %P, align 4, !tbaa !0 + br label %bb1 + +bb1: ; preds = %entry, %bb + %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ] + %2 = load i32* %P, align 4, !tbaa !0 + %3 = icmp sgt i32 %2, 36 + br i1 %3, label %bb3, label %bb2 + +bb2: ; preds = %bb1 + %4 = tail call i32 (...)* @f2() nounwind + ret i32 %res.0 + +bb3: ; preds = %bb1 +; CHECK: bb3: +; CHECK: %res.01 = phi i32 [ 1, %bb1.thread ], [ 0, %bb1 ] +; CHECK: ret i32 %res.01 + ret i32 %res.0 +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} + diff --git a/test/Transforms/LoopSimplify/2012-03-20-indirectbr.ll b/test/Transforms/LoopSimplify/2012-03-20-indirectbr.ll new file mode 100644 index 0000000..9c805da --- /dev/null +++ b/test/Transforms/LoopSimplify/2012-03-20-indirectbr.ll @@ -0,0 +1,41 @@ +; RUN: opt < %s -loop-simplify -S | FileCheck %s + +; Make sure the preheader exists. +; CHECK: sw.bb103: +; CHECK: indirectbr {{.*}}label %while.cond112 +; CHECK: while.cond112: +; But the tail is not split. +; CHECK: for.body: +; CHECK: indirectbr {{.*}}label %while.cond112 +define fastcc void @build_regex_nfa() nounwind uwtable ssp { +entry: + indirectbr i8* blockaddress(@build_regex_nfa, %while.cond), [label %while.cond] + +while.cond: ; preds = %if.then439, %entry + indirectbr i8* blockaddress(@build_regex_nfa, %sw.bb103), [label %do.body785, label %sw.bb103] + +sw.bb103: ; preds = %while.body + indirectbr i8* blockaddress(@build_regex_nfa, %while.cond112), [label %while.cond112] + +while.cond112: ; preds = %for.body, %for.cond.preheader, %sw.bb103 + %pc.0 = phi i8 [ -1, %sw.bb103 ], [ 0, %for.body ], [ %pc.0, %for.cond.preheader ] + indirectbr i8* blockaddress(@build_regex_nfa, %Lsetdone), [label %sw.bb118, label %Lsetdone] + +sw.bb118: ; preds = %while.cond112 + indirectbr i8* blockaddress(@build_regex_nfa, %for.cond.preheader), [label %Lerror.loopexit, label %for.cond.preheader] + +for.cond.preheader: ; preds = %sw.bb118 + indirectbr i8* blockaddress(@build_regex_nfa, %for.body), [label %while.cond112, label %for.body] + +for.body: ; preds = %for.body, %for.cond.preheader + indirectbr i8* blockaddress(@build_regex_nfa, %for.body), [label %while.cond112, label %for.body] + +Lsetdone: ; preds = %while.cond112 + unreachable + +do.body785: ; preds = %while.cond, %while.body + ret void + +Lerror.loopexit: ; preds = %sw.bb118 + unreachable +} diff --git a/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll new file mode 100644 index 0000000..0172492 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll @@ -0,0 +1,155 @@ +; RUN: opt -loop-reduce -S < %s | FileCheck %s +; +; <rdar://problem/11049788> Segmentation fault: 11 in LoopStrengthReduce + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +; IVUsers should not consider tmp128 a valid user because it is not in a +; simplified loop nest. +; CHECK: @nopreheader +; CHECK: for.cond: +; CHECK: %tmp128 = add i64 %0, %indvar65 +define void @nopreheader(i8* %cmd) nounwind ssp { +entry: + indirectbr i8* undef, [label %while.cond] + +while.cond: ; preds = %while.body, %entry + %0 = phi i64 [ %indvar.next48, %while.body ], [ 0, %entry ] + indirectbr i8* undef, [label %while.end, label %while.body] + +while.body: ; preds = %lor.rhs, %lor.lhs.false17, %lor.lhs.false11, %lor.lhs.false, %land.rhs + %indvar.next48 = add i64 %0, 1 + indirectbr i8* undef, [label %while.cond] + +while.end: ; preds = %lor.rhs, %while.cond + indirectbr i8* undef, [label %if.end152] + +if.end152: ; preds = %lor.lhs.false144, %if.end110 + indirectbr i8* undef, [label %lor.lhs.false184, label %for.cond] + +lor.lhs.false184: ; preds = %lor.lhs.false177 + indirectbr i8* undef, [label %return, label %for.cond] + +for.cond: ; preds = %for.inc, %lor.lhs.false184, %if.end152 + %indvar65 = phi i64 [ %indvar.next66, %for.inc ], [ 0, %lor.lhs.false184 ], [ 0, %if.end152 ] + %tmp128 = add i64 %0, %indvar65 + %s.4 = getelementptr i8* %cmd, i64 %tmp128 + %tmp195 = load i8* %s.4, align 1 + indirectbr i8* undef, [label %return, label %land.rhs198] + +land.rhs198: ; preds = %for.cond + indirectbr i8* undef, [label %return, label %for.inc] + +for.inc: ; preds = %lor.rhs234, %land.lhs.true228, %land.lhs.true216, %land.lhs.true204 + %indvar.next66 = add i64 %indvar65, 1 + indirectbr i8* undef, [label %for.cond] + +return: ; preds = %if.end677, %doshell, %if.then96 + ret void +} + +; Another case with a dominating loop that does not contain the IV +; User. Just make sure it doesn't assert. +define void @nopreheader2() nounwind ssp { +entry: + indirectbr i8* undef, [label %while.cond, label %return] + +while.cond: ; preds = %while.cond.backedge, %entry + indirectbr i8* undef, [label %while.cond.backedge, label %lor.rhs] + +lor.rhs: ; preds = %while.cond + indirectbr i8* undef, [label %while.cond.backedge, label %while.end] + +while.cond.backedge: ; preds = %lor.rhs, %while.cond + indirectbr i8* undef, [label %while.cond] + +while.end: ; preds = %lor.rhs + indirectbr i8* undef, [label %if.then18, label %return] + +if.then18: ; preds = %while.end + indirectbr i8* undef, [label %if.end35, label %lor.lhs.false] + +lor.lhs.false: ; preds = %if.then18 + indirectbr i8* undef, [label %if.end35, label %return] + +if.end35: ; preds = %lor.lhs.false, %if.then18 + indirectbr i8* undef, [label %while.cond36] + +while.cond36: ; preds = %while.body49, %if.end35 + %0 = phi i64 [ %indvar.next13, %while.body49 ], [ 0, %if.end35 ] + indirectbr i8* undef, [label %while.body49, label %lor.rhs42] + +lor.rhs42: ; preds = %while.cond36 + indirectbr i8* undef, [label %while.body49, label %while.end52] + +while.body49: ; preds = %lor.rhs42, %while.cond36 + %indvar.next13 = add i64 %0, 1 + indirectbr i8* undef, [label %while.cond36] + +while.end52: ; preds = %lor.rhs42 + indirectbr i8* undef, [label %land.lhs.true, label %return] + +land.lhs.true: ; preds = %while.end52 + indirectbr i8* undef, [label %while.cond66.preheader, label %return] + +while.cond66.preheader: ; preds = %land.lhs.true + indirectbr i8* undef, [label %while.cond66] + +while.cond66: ; preds = %while.body77, %while.cond66.preheader + indirectbr i8* undef, [label %land.rhs, label %while.cond81.preheader] + +land.rhs: ; preds = %while.cond66 + indirectbr i8* undef, [label %while.body77, label %while.cond81.preheader] + +while.cond81.preheader: ; preds = %land.rhs, %while.cond66 + %tmp45 = add i64 undef, %0 + %tmp46 = add i64 %tmp45, undef + indirectbr i8* undef, [label %while.cond81] + +while.body77: ; preds = %land.rhs + indirectbr i8* undef, [label %while.cond66] + +while.cond81: ; preds = %while.body94, %while.cond81.preheader + %tmp25 = add i64 %tmp46, undef + indirectbr i8* undef, [label %while.body94, label %lor.rhs87] + +lor.rhs87: ; preds = %while.cond81 + indirectbr i8* undef, [label %while.body94, label %return] + +while.body94: ; preds = %lor.rhs87, %while.cond81 + indirectbr i8* undef, [label %while.cond81] + +return: ; preds = %if.end216, %land.lhs.true183, %land.lhs.true, %while.end52, %lor.lhs.false, %while.end, %entry + ret void +} + +; Test a phi operand IV User dominated by a no-preheader loop. +define void @nopreheader3() nounwind uwtable ssp align 2 { +entry: + indirectbr i8* blockaddress(@nopreheader3, %if.end10), [label %if.end22, label %if.end10] + +if.end10: ; preds = %entry + indirectbr i8* blockaddress(@nopreheader3, %if.end6.i), [label %if.end22, label %if.end6.i] + +if.end6.i: ; preds = %if.end10 + indirectbr i8* blockaddress(@nopreheader3, %while.cond2.preheader.i.i), [label %if.then12, label %while.cond2.preheader.i.i] + +while.cond2.preheader.i.i: ; preds = %while.end.i18.i, %if.end6.i + indirectbr i8* blockaddress(@nopreheader3, %while.cond2.i.i), [label %while.cond2.i.i] + +while.cond2.i.i: ; preds = %while.cond2.i.i, %while.cond2.preheader.i.i + %i1.1.i14.i = phi i32 [ %add.i15.i, %while.cond2.i.i ], [ undef, %while.cond2.preheader.i.i ] + %add.i15.i = add nsw i32 %i1.1.i14.i, undef + indirectbr i8* blockaddress(@nopreheader3, %while.end.i18.i), [label %while.cond2.i.i, label %while.end.i18.i] + +while.end.i18.i: ; preds = %while.cond2.i.i + indirectbr i8* blockaddress(@nopreheader3, %while.cond2.preheader.i.i), [label %if.then12, label %while.cond2.preheader.i.i] + +if.then12: ; preds = %while.end.i18.i, %if.end6.i + %i1.0.lcssa.i.i = phi i32 [ undef, %if.end6.i ], [ %i1.1.i14.i, %while.end.i18.i ] + indirectbr i8* blockaddress(@nopreheader3, %if.end22), [label %if.end22] + +if.end22: ; preds = %if.then12, %if.end10, %entry + ret void +} diff --git a/test/Transforms/LoopStrengthReduce/2011-11-29-postincphi.ll b/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll index cb23ad0..cb23ad0 100644 --- a/test/Transforms/LoopStrengthReduce/2011-11-29-postincphi.ll +++ b/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll diff --git a/test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll b/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll index 5108650..5108650 100644 --- a/test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll +++ b/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll diff --git a/test/Transforms/ObjCARC/basic.ll b/test/Transforms/ObjCARC/basic.ll index 552f4e0..08bd8c0 100644 --- a/test/Transforms/ObjCARC/basic.ll +++ b/test/Transforms/ObjCARC/basic.ll @@ -1721,6 +1721,82 @@ define void @test61() { ret void } +; Delete a retain matched by releases when one is inside the loop and the +; other is outside the loop. + +; CHECK: define void @test62( +; CHECK-NOT: @objc_ +; CHECK: } +define void @test62(i8* %x, i1* %p) nounwind { +entry: + br label %loop + +loop: + call i8* @objc_retain(i8* %x) + %q = load i1* %p + br i1 %q, label %loop.more, label %exit + +loop.more: + call void @objc_release(i8* %x) + br label %loop + +exit: + call void @objc_release(i8* %x) + ret void +} + +; Like test62 but with no release in exit. +; Don't delete anything! + +; CHECK: define void @test63( +; CHECK: loop: +; CHECK: tail call i8* @objc_retain(i8* %x) +; CHECK: loop.more: +; CHECK: call void @objc_release(i8* %x) +; CHECK: } +define void @test63(i8* %x, i1* %p) nounwind { +entry: + br label %loop + +loop: + call i8* @objc_retain(i8* %x) + %q = load i1* %p + br i1 %q, label %loop.more, label %exit + +loop.more: + call void @objc_release(i8* %x) + br label %loop + +exit: + ret void +} + +; Like test62 but with no release in loop.more. +; Don't delete anything! + +; CHECK: define void @test64( +; CHECK: loop: +; CHECK: tail call i8* @objc_retain(i8* %x) +; CHECK: exit: +; CHECK: call void @objc_release(i8* %x) +; CHECK: } +define void @test64(i8* %x, i1* %p) nounwind { +entry: + br label %loop + +loop: + call i8* @objc_retain(i8* %x) + %q = load i1* %p + br i1 %q, label %loop.more, label %exit + +loop.more: + br label %loop + +exit: + call void @objc_release(i8* %x) + ret void +} + declare void @bar(i32 ()*) ; A few real-world testcases. diff --git a/test/Transforms/ObjCARC/invoke.ll b/test/Transforms/ObjCARC/invoke.ll index cf971e4..9e26209 100644 --- a/test/Transforms/ObjCARC/invoke.ll +++ b/test/Transforms/ObjCARC/invoke.ll @@ -2,6 +2,7 @@ declare i8* @objc_retain(i8*) declare void @objc_release(i8*) +declare i8* @objc_retainAutoreleasedReturnValue(i8*) declare i8* @objc_msgSend(i8*, i8*, ...) declare void @use_pointer(i8*) declare void @callee() @@ -68,6 +69,41 @@ done: ret void } +; The optimizer should ignore invoke unwind paths consistently. +; PR12265 + +; CHECK: define void @test2() { +; CHECK: invoke.cont: +; CHECK-NEXT: call i8* @objc_retain +; CHEK-NOT: @objc +; CHECK: finally.cont: +; CHECK-NEXT: call void @objc_release +; CHEK-NOT: @objc +; CHECK: finally.rethrow: +; CHEK-NOT: @objc +; CHECK: } +define void @test2() { +entry: + %call = invoke i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* ()*)() + to label %invoke.cont unwind label %finally.rethrow, !clang.arc.no_objc_arc_exceptions !0 + +invoke.cont: ; preds = %entry + %tmp1 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %call) nounwind + call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void ()*)(), !clang.arc.no_objc_arc_exceptions !0 + invoke void @use_pointer(i8* %call) + to label %finally.cont unwind label %finally.rethrow, !clang.arc.no_objc_arc_exceptions !0 + +finally.cont: ; preds = %invoke.cont + tail call void @objc_release(i8* %call) nounwind, !clang.imprecise_release !0 + ret void + +finally.rethrow: ; preds = %invoke.cont, %entry + %tmp2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__objc_personality_v0 to i8*) + catch i8* null + unreachable +} + declare i32 @__gxx_personality_v0(...) +declare i32 @__objc_personality_v0(...) !0 = metadata !{} diff --git a/test/Transforms/ObjCARC/nested.ll b/test/Transforms/ObjCARC/nested.ll index 9eada8a..a618a21 100644 --- a/test/Transforms/ObjCARC/nested.ll +++ b/test/Transforms/ObjCARC/nested.ll @@ -484,12 +484,14 @@ forcoll.empty: ret void } -; Delete a nested retain+release pair. +; TODO: Delete a nested retain+release pair. +; The optimizer currently can't do this, because of a split loop backedge. +; See test9b for the same testcase without a split backedge. ; CHECK: define void @test9( ; CHECK: call i8* @objc_retain ; CHECK: call i8* @objc_retain -; CHECK-NOT: @objc_retain +; CHECK: call i8* @objc_retain ; CHECK: } define void @test9() nounwind { entry: @@ -551,13 +553,79 @@ forcoll.empty: ret void } -; Delete a nested retain+release pair. +; Like test9, but without a split backedge. This we can optimize. -; CHECK: define void @test10( +; CHECK: define void @test9b( ; CHECK: call i8* @objc_retain ; CHECK: call i8* @objc_retain ; CHECK-NOT: @objc_retain ; CHECK: } +define void @test9b() nounwind { +entry: + %state.ptr = alloca %struct.__objcFastEnumerationState, align 8 + %items.ptr = alloca [16 x i8*], align 8 + %call = call i8* @returner() + %0 = call i8* @objc_retainAutoreleasedReturnValue(i8* %call) nounwind + %call1 = call i8* @returner() + %1 = call i8* @objc_retainAutoreleasedReturnValue(i8* %call1) nounwind + %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8* + call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false) + %2 = call i8* @objc_retain(i8* %0) nounwind + %tmp3 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8 + %call4 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp3, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16) + %iszero = icmp eq i64 %call4, 0 + br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit + +forcoll.loopinit: + %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2 + %mutationsptr = load i64** %mutationsptr.ptr, align 8 + %forcoll.initial-mutations = load i64* %mutationsptr, align 8 + br label %forcoll.loopbody.outer + +forcoll.loopbody.outer: + %forcoll.count.ph = phi i64 [ %call4, %forcoll.loopinit ], [ %call7, %forcoll.refetch ] + %tmp9 = icmp ugt i64 %forcoll.count.ph, 1 + %umax = select i1 %tmp9, i64 %forcoll.count.ph, i64 1 + br label %forcoll.loopbody + +forcoll.loopbody: + %forcoll.index = phi i64 [ %phitmp, %forcoll.notmutated ], [ 0, %forcoll.loopbody.outer ] + %mutationsptr5 = load i64** %mutationsptr.ptr, align 8 + %statemutations = load i64* %mutationsptr5, align 8 + %3 = icmp eq i64 %statemutations, %forcoll.initial-mutations + br i1 %3, label %forcoll.notmutated, label %forcoll.mutated + +forcoll.mutated: + call void @objc_enumerationMutation(i8* %2) + br label %forcoll.notmutated + +forcoll.notmutated: + %phitmp = add i64 %forcoll.index, 1 + %exitcond = icmp eq i64 %phitmp, %umax + br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody + +forcoll.refetch: + %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8 + %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16) + %4 = icmp eq i64 %call7, 0 + br i1 %4, label %forcoll.empty, label %forcoll.loopbody.outer + +forcoll.empty: + call void @objc_release(i8* %2) nounwind + call void @objc_release(i8* %1) nounwind, !clang.imprecise_release !0 + call void @objc_release(i8* %0) nounwind, !clang.imprecise_release !0 + ret void +} + +; TODO: Delete a nested retain+release pair. +; The optimizer currently can't do this, because of a split loop backedge. +; See test10b for the same testcase without a split backedge. + +; CHECK: define void @test10( +; CHECK: call i8* @objc_retain +; CHECK: call i8* @objc_retain +; CHECK: call i8* @objc_retain +; CHECK: } define void @test10() nounwind { entry: %state.ptr = alloca %struct.__objcFastEnumerationState, align 8 @@ -618,3 +686,68 @@ forcoll.empty: call void @objc_release(i8* %0) nounwind, !clang.imprecise_release !0 ret void } + +; Like test10, but without a split backedge. This we can optimize. + +; CHECK: define void @test10b( +; CHECK: call i8* @objc_retain +; CHECK: call i8* @objc_retain +; CHECK-NOT: @objc_retain +; CHECK: } +define void @test10b() nounwind { +entry: + %state.ptr = alloca %struct.__objcFastEnumerationState, align 8 + %items.ptr = alloca [16 x i8*], align 8 + %call = call i8* @returner() + %0 = call i8* @objc_retainAutoreleasedReturnValue(i8* %call) nounwind + %call1 = call i8* @returner() + %1 = call i8* @objc_retainAutoreleasedReturnValue(i8* %call1) nounwind + call void @callee() + %tmp = bitcast %struct.__objcFastEnumerationState* %state.ptr to i8* + call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 8, i1 false) + %2 = call i8* @objc_retain(i8* %0) nounwind + %tmp3 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8 + %call4 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp3, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16) + %iszero = icmp eq i64 %call4, 0 + br i1 %iszero, label %forcoll.empty, label %forcoll.loopinit + +forcoll.loopinit: + %mutationsptr.ptr = getelementptr inbounds %struct.__objcFastEnumerationState* %state.ptr, i64 0, i32 2 + %mutationsptr = load i64** %mutationsptr.ptr, align 8 + %forcoll.initial-mutations = load i64* %mutationsptr, align 8 + br label %forcoll.loopbody.outer + +forcoll.loopbody.outer: + %forcoll.count.ph = phi i64 [ %call4, %forcoll.loopinit ], [ %call7, %forcoll.refetch ] + %tmp9 = icmp ugt i64 %forcoll.count.ph, 1 + %umax = select i1 %tmp9, i64 %forcoll.count.ph, i64 1 + br label %forcoll.loopbody + +forcoll.loopbody: + %forcoll.index = phi i64 [ %phitmp, %forcoll.notmutated ], [ 0, %forcoll.loopbody.outer ] + %mutationsptr5 = load i64** %mutationsptr.ptr, align 8 + %statemutations = load i64* %mutationsptr5, align 8 + %3 = icmp eq i64 %statemutations, %forcoll.initial-mutations + br i1 %3, label %forcoll.notmutated, label %forcoll.mutated + +forcoll.mutated: + call void @objc_enumerationMutation(i8* %2) + br label %forcoll.notmutated + +forcoll.notmutated: + %phitmp = add i64 %forcoll.index, 1 + %exitcond = icmp eq i64 %phitmp, %umax + br i1 %exitcond, label %forcoll.refetch, label %forcoll.loopbody + +forcoll.refetch: + %tmp6 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8 + %call7 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*, %struct.__objcFastEnumerationState*, [16 x i8*]*, i64)*)(i8* %2, i8* %tmp6, %struct.__objcFastEnumerationState* %state.ptr, [16 x i8*]* %items.ptr, i64 16) + %4 = icmp eq i64 %call7, 0 + br i1 %4, label %forcoll.empty, label %forcoll.loopbody.outer + +forcoll.empty: + call void @objc_release(i8* %2) nounwind + call void @objc_release(i8* %1) nounwind, !clang.imprecise_release !0 + call void @objc_release(i8* %0) nounwind, !clang.imprecise_release !0 + ret void +} diff --git a/test/Transforms/ObjCARC/pr12270.ll b/test/Transforms/ObjCARC/pr12270.ll new file mode 100644 index 0000000..30610f8 --- /dev/null +++ b/test/Transforms/ObjCARC/pr12270.ll @@ -0,0 +1,15 @@ +; RUN: opt -disable-output -objc-arc-contract %s +; test that we don't crash on unreachable code +%2 = type opaque + +define void @_i_Test__foo(%2 *%x) { +entry: + unreachable + +return: ; No predecessors! + %bar = bitcast %2* %x to i8* + %foo = call i8* @objc_autoreleaseReturnValue(i8* %bar) nounwind + ret void +} + +declare i8* @objc_autoreleaseReturnValue(i8*) diff --git a/test/Transforms/ScalarRepl/negative-memset.ll b/test/Transforms/ScalarRepl/negative-memset.ll new file mode 100644 index 0000000..e52ab46 --- /dev/null +++ b/test/Transforms/ScalarRepl/negative-memset.ll @@ -0,0 +1,20 @@ +; PR12202 +; RUN: opt < %s -scalarrepl -S +; Ensure that we do not hang or crash when feeding a negative value to memset + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32" +target triple = "i686-pc-win32" + +define i32 @test() nounwind { +entry: + %retval = alloca i32, align 4 + %buff = alloca [1 x i8], align 1 + store i32 0, i32* %retval + %0 = bitcast [1 x i8]* %buff to i8* + call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 1, i32 1, i1 false) + %arraydecay = getelementptr inbounds [1 x i8]* %buff, i32 0, i32 0 + call void @llvm.memset.p0i8.i32(i8* %arraydecay, i8 -1, i32 -8, i32 1, i1 false) ; Negative 8! + ret i32 0 +} + +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind diff --git a/test/lit.site.cfg.in b/test/lit.site.cfg.in index 8b81186..4fdfb04 100644 --- a/test/lit.site.cfg.in +++ b/test/lit.site.cfg.in @@ -9,6 +9,7 @@ config.enable_shared = @ENABLE_SHARED@ config.enable_assertions = @ENABLE_ASSERTIONS@ config.targets_to_build = "@TARGETS_TO_BUILD@" config.llvm_bindings = "@LLVM_BINDINGS@" +config.host_os = "@HOST_OS@" # Support substitution of the tools_dir with user parameters. This is # used when we can't determine the tool dir at configuration time. |