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Diffstat (limited to 'utils/TableGen/X86RecognizableInstr.cpp')
-rw-r--r--utils/TableGen/X86RecognizableInstr.cpp195
1 files changed, 124 insertions, 71 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 9b8092f..5f12965 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -28,54 +28,65 @@ using namespace llvm;
MAP(C2, 34) \
MAP(C3, 35) \
MAP(C4, 36) \
- MAP(C8, 37) \
- MAP(C9, 38) \
- MAP(CA, 39) \
- MAP(CB, 40) \
- MAP(CF, 41) \
- MAP(D0, 42) \
- MAP(D1, 43) \
- MAP(D4, 44) \
- MAP(D5, 45) \
- MAP(D6, 46) \
- MAP(D7, 47) \
- MAP(D8, 48) \
- MAP(D9, 49) \
- MAP(DA, 50) \
- MAP(DB, 51) \
- MAP(DC, 52) \
- MAP(DD, 53) \
- MAP(DE, 54) \
- MAP(DF, 55) \
- MAP(E0, 56) \
- MAP(E1, 57) \
- MAP(E2, 58) \
- MAP(E3, 59) \
- MAP(E4, 60) \
- MAP(E5, 61) \
- MAP(E8, 62) \
- MAP(E9, 63) \
- MAP(EA, 64) \
- MAP(EB, 65) \
- MAP(EC, 66) \
- MAP(ED, 67) \
- MAP(EE, 68) \
- MAP(F0, 69) \
- MAP(F1, 70) \
- MAP(F2, 71) \
- MAP(F3, 72) \
- MAP(F4, 73) \
- MAP(F5, 74) \
- MAP(F6, 75) \
- MAP(F7, 76) \
- MAP(F8, 77) \
- MAP(F9, 78) \
- MAP(FA, 79) \
- MAP(FB, 80) \
- MAP(FC, 81) \
- MAP(FD, 82) \
- MAP(FE, 83) \
- MAP(FF, 84)
+ MAP(C5, 37) \
+ MAP(C6, 38) \
+ MAP(C7, 39) \
+ MAP(C8, 40) \
+ MAP(C9, 41) \
+ MAP(CA, 42) \
+ MAP(CB, 43) \
+ MAP(CC, 44) \
+ MAP(CD, 45) \
+ MAP(CE, 46) \
+ MAP(CF, 47) \
+ MAP(D0, 48) \
+ MAP(D1, 49) \
+ MAP(D2, 50) \
+ MAP(D3, 51) \
+ MAP(D4, 52) \
+ MAP(D5, 53) \
+ MAP(D6, 54) \
+ MAP(D7, 55) \
+ MAP(D8, 56) \
+ MAP(D9, 57) \
+ MAP(DA, 58) \
+ MAP(DB, 59) \
+ MAP(DC, 60) \
+ MAP(DD, 61) \
+ MAP(DE, 62) \
+ MAP(DF, 63) \
+ MAP(E0, 64) \
+ MAP(E1, 65) \
+ MAP(E2, 66) \
+ MAP(E3, 67) \
+ MAP(E4, 68) \
+ MAP(E5, 69) \
+ MAP(E6, 70) \
+ MAP(E7, 71) \
+ MAP(E8, 72) \
+ MAP(E9, 73) \
+ MAP(EA, 74) \
+ MAP(EB, 75) \
+ MAP(EC, 76) \
+ MAP(ED, 77) \
+ MAP(EE, 78) \
+ MAP(EF, 79) \
+ MAP(F0, 80) \
+ MAP(F1, 81) \
+ MAP(F2, 82) \
+ MAP(F3, 83) \
+ MAP(F4, 84) \
+ MAP(F5, 85) \
+ MAP(F6, 86) \
+ MAP(F7, 87) \
+ MAP(F8, 88) \
+ MAP(F9, 89) \
+ MAP(FA, 90) \
+ MAP(FB, 91) \
+ MAP(FC, 92) \
+ MAP(FD, 93) \
+ MAP(FE, 94) \
+ MAP(FF, 95)
// A clone of X86 since we can't depend on something that is generated.
namespace X86Local {
@@ -119,6 +130,10 @@ namespace X86Local {
enum {
OpSize16 = 1, OpSize32 = 2
};
+
+ enum {
+ AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
+ };
}
using namespace X86Disassembler;
@@ -194,7 +209,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
Encoding = byteFromRec(Rec, "OpEncBits");
OpSize = byteFromRec(Rec, "OpSizeBits");
- HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
+ AdSize = byteFromRec(Rec, "AdSizeBits");
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
@@ -401,16 +416,20 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
- } else if (Is64Bit || HasREX_WPrefix) {
+ } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
insnContext = IC_64BIT_REXW_OPSIZE;
+ else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
+ insnContext = IC_64BIT_REXW_ADSIZE;
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
insnContext = IC_64BIT_XD_OPSIZE;
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
insnContext = IC_64BIT_XS_OPSIZE;
+ else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
+ insnContext = IC_64BIT_OPSIZE_ADSIZE;
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
insnContext = IC_64BIT_OPSIZE;
- else if (HasAdSizePrefix)
+ else if (AdSize == X86Local::AdSize32)
insnContext = IC_64BIT_ADSIZE;
else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
insnContext = IC_64BIT_REXW_XS;
@@ -429,9 +448,11 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_XD_OPSIZE;
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
insnContext = IC_XS_OPSIZE;
+ else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
+ insnContext = IC_OPSIZE_ADSIZE;
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
insnContext = IC_OPSIZE;
- else if (HasAdSizePrefix)
+ else if (AdSize == X86Local::AdSize16)
insnContext = IC_ADSIZE;
else if (OpPrefix == X86Local::XD)
insnContext = IC_XD;
@@ -504,7 +525,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
- if (OperandList[operandIndex].Constraints.size()) {
+ if (!OperandList[operandIndex].Constraints.empty()) {
const CGIOperandList::ConstraintInfo &Constraint =
OperandList[operandIndex].Constraints[0];
if (Constraint.isTied()) {
@@ -793,9 +814,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
// Special cases where the LLVM tables are not complete
#define MAP(from, to) \
- case X86Local::MRM_##from: \
- filter = new ExactFilter(0x##from); \
- break;
+ case X86Local::MRM_##from:
OpcodeType opcodeType = (OpcodeType)-1;
@@ -844,12 +863,21 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
break;
MRM_MAPPING
+ filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \
+ break;
} // switch (Form)
opcodeToSet = Opcode;
break;
} // switch (OpMap)
+ unsigned AddressSize = 0;
+ switch (AdSize) {
+ case X86Local::AdSize16: AddressSize = 16; break;
+ case X86Local::AdSize32: AddressSize = 32; break;
+ case X86Local::AdSize64: AddressSize = 64; break;
+ }
+
assert(opcodeType != (OpcodeType)-1 &&
"Opcode type not set");
assert(filter && "Filter not set");
@@ -867,13 +895,13 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
insnContext(),
currentOpcode,
*filter,
- UID, Is32Bit, IgnoresVEX_L);
+ UID, Is32Bit, IgnoresVEX_L, AddressSize);
} else {
tables.setTableFields(opcodeType,
insnContext(),
opcodeToSet,
*filter,
- UID, Is32Bit, IgnoresVEX_L);
+ UID, Is32Bit, IgnoresVEX_L, AddressSize);
}
delete filter;
@@ -915,6 +943,8 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("GR64", TYPE_R64)
TYPE("i8mem", TYPE_M8)
TYPE("i8imm", TYPE_IMM8)
+ TYPE("u8imm", TYPE_UIMM8)
+ TYPE("i32u8imm", TYPE_UIMM8)
TYPE("GR8", TYPE_R8)
TYPE("VR128", TYPE_XMM128)
TYPE("VR128X", TYPE_XMM128)
@@ -937,17 +967,19 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("i16imm_pcrel", TYPE_REL16)
TYPE("i32imm_pcrel", TYPE_REL32)
TYPE("SSECC", TYPE_IMM3)
+ TYPE("XOPCC", TYPE_IMM3)
TYPE("AVXCC", TYPE_IMM5)
+ TYPE("AVX512ICC", TYPE_AVX512ICC)
TYPE("AVX512RC", TYPE_IMM32)
- TYPE("brtarget", TYPE_RELv)
- TYPE("uncondbrtarget", TYPE_RELv)
+ TYPE("brtarget32", TYPE_RELv)
+ TYPE("brtarget16", TYPE_RELv)
TYPE("brtarget8", TYPE_REL8)
TYPE("f80mem", TYPE_M80FP)
- TYPE("lea32mem", TYPE_LEA)
TYPE("lea64_32mem", TYPE_LEA)
TYPE("lea64mem", TYPE_LEA)
TYPE("VR64", TYPE_MM64)
TYPE("i64imm", TYPE_IMMv)
+ TYPE("anymem", TYPE_M)
TYPE("opaque32mem", TYPE_M1616)
TYPE("opaque48mem", TYPE_M1632)
TYPE("opaque80mem", TYPE_M1664)
@@ -963,10 +995,17 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("dstidx16", TYPE_DSTIDX16)
TYPE("dstidx32", TYPE_DSTIDX32)
TYPE("dstidx64", TYPE_DSTIDX64)
- TYPE("offset8", TYPE_MOFFS8)
- TYPE("offset16", TYPE_MOFFS16)
- TYPE("offset32", TYPE_MOFFS32)
- TYPE("offset64", TYPE_MOFFS64)
+ TYPE("offset16_8", TYPE_MOFFS8)
+ TYPE("offset16_16", TYPE_MOFFS16)
+ TYPE("offset16_32", TYPE_MOFFS32)
+ TYPE("offset32_8", TYPE_MOFFS8)
+ TYPE("offset32_16", TYPE_MOFFS16)
+ TYPE("offset32_32", TYPE_MOFFS32)
+ TYPE("offset32_64", TYPE_MOFFS64)
+ TYPE("offset64_8", TYPE_MOFFS8)
+ TYPE("offset64_16", TYPE_MOFFS16)
+ TYPE("offset64_32", TYPE_MOFFS32)
+ TYPE("offset64_64", TYPE_MOFFS64)
TYPE("VR256", TYPE_XMM256)
TYPE("VR256X", TYPE_XMM256)
TYPE("VR512", TYPE_XMM512)
@@ -1010,7 +1049,9 @@ RecognizableInstr::immediateEncodingFromString(const std::string &s,
}
ENCODING("i32i8imm", ENCODING_IB)
ENCODING("SSECC", ENCODING_IB)
+ ENCODING("XOPCC", ENCODING_IB)
ENCODING("AVXCC", ENCODING_IB)
+ ENCODING("AVX512ICC", ENCODING_IB)
ENCODING("AVX512RC", ENCODING_IB)
ENCODING("i16imm", ENCODING_Iv)
ENCODING("i16i8imm", ENCODING_IB)
@@ -1018,6 +1059,8 @@ RecognizableInstr::immediateEncodingFromString(const std::string &s,
ENCODING("i64i32imm", ENCODING_ID)
ENCODING("i64i8imm", ENCODING_IB)
ENCODING("i8imm", ENCODING_IB)
+ ENCODING("u8imm", ENCODING_IB)
+ ENCODING("i32u8imm", ENCODING_IB)
// This is not a typo. Instructions like BLENDVPD put
// register IDs in 8-bit immediates nowadays.
ENCODING("FR32", ENCODING_IB)
@@ -1153,9 +1196,9 @@ RecognizableInstr::memoryEncodingFromString(const std::string &s,
ENCODING("i256mem", ENCODING_RM)
ENCODING("i512mem", ENCODING_RM)
ENCODING("f80mem", ENCODING_RM)
- ENCODING("lea32mem", ENCODING_RM)
ENCODING("lea64_32mem", ENCODING_RM)
ENCODING("lea64mem", ENCODING_RM)
+ ENCODING("anymem", ENCODING_RM)
ENCODING("opaque32mem", ENCODING_RM)
ENCODING("opaque48mem", ENCODING_RM)
ENCODING("opaque80mem", ENCODING_RM)
@@ -1186,16 +1229,26 @@ RecognizableInstr::relocationEncodingFromString(const std::string &s,
ENCODING("i64i32imm", ENCODING_ID)
ENCODING("i64i8imm", ENCODING_IB)
ENCODING("i8imm", ENCODING_IB)
+ ENCODING("u8imm", ENCODING_IB)
+ ENCODING("i32u8imm", ENCODING_IB)
ENCODING("i64i32imm_pcrel", ENCODING_ID)
ENCODING("i16imm_pcrel", ENCODING_IW)
ENCODING("i32imm_pcrel", ENCODING_ID)
- ENCODING("brtarget", ENCODING_Iv)
+ ENCODING("brtarget32", ENCODING_Iv)
+ ENCODING("brtarget16", ENCODING_Iv)
ENCODING("brtarget8", ENCODING_IB)
ENCODING("i64imm", ENCODING_IO)
- ENCODING("offset8", ENCODING_Ia)
- ENCODING("offset16", ENCODING_Ia)
- ENCODING("offset32", ENCODING_Ia)
- ENCODING("offset64", ENCODING_Ia)
+ ENCODING("offset16_8", ENCODING_Ia)
+ ENCODING("offset16_16", ENCODING_Ia)
+ ENCODING("offset16_32", ENCODING_Ia)
+ ENCODING("offset32_8", ENCODING_Ia)
+ ENCODING("offset32_16", ENCODING_Ia)
+ ENCODING("offset32_32", ENCODING_Ia)
+ ENCODING("offset32_64", ENCODING_Ia)
+ ENCODING("offset64_8", ENCODING_Ia)
+ ENCODING("offset64_16", ENCODING_Ia)
+ ENCODING("offset64_32", ENCODING_Ia)
+ ENCODING("offset64_64", ENCODING_Ia)
ENCODING("srcidx8", ENCODING_SI)
ENCODING("srcidx16", ENCODING_SI)
ENCODING("srcidx32", ENCODING_SI)
generated by cgit v1.1 at 2024-12-22 11:31:23 +0000