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* Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd2012-05-043-139/+272
* Pacify GCC's -Wreturn-typeMatt Beaumont-Gay2012-05-041-0/+1
* Factor the computation of input and output sets into a public interfaceChandler Carruth2012-05-042-37/+45
* Rather than trying to gracefully handle input sequences with repeatedChandler Carruth2012-05-041-1/+1
* Fix a goof with my previous commit by completely returning when weChandler Carruth2012-05-041-1/+1
* Hoist a safety assert from the extraction method into the constructionChandler Carruth2012-05-041-9/+13
* Move the CodeExtractor utility to a dedicated header file / source file,Chandler Carruth2012-05-046-220/+225
* Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg2012-05-043-12/+23
* Fix some loops to match coding standards. No functional change intended.Craig Topper2012-05-041-6/+8
* Fix up some spacing. No functional change.Craig Topper2012-05-041-6/+6
* Simplify broadcast lowering code. No functional change intended.Craig Topper2012-05-041-17/+7
* Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.Craig Topper2012-05-042-5/+16
* Add 'landingpad' instructions to the list of instructions to ignore.Bill Wendling2012-05-041-7/+9
* Simplify shuffle narrowing code a bit. No functional change intended.Craig Topper2012-05-041-22/+16
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-047-125/+30
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-044-89/+0
* Pass -fcolor-diagnostics when it is supported. This makes a difference whenRafael Espindola2012-05-041-0/+4
* Use SuperRegClassIterator for findRepresentativeClass().Jakob Stoklund Olesen2012-05-042-30/+15
* Initialize SparcInstrInfo before SparcTargetLowering.Jakob Stoklund Olesen2012-05-042-2/+3
* Add a SuperRegClassIterator class.Jakob Stoklund Olesen2012-05-042-15/+69
* A pile of long over-due refactorings here. There are some very, *very*Chandler Carruth2012-05-045-50/+40
* Add a FoldingSetVector datastructure which is analogous to a SetVector,Chandler Carruth2012-05-031-0/+105
* PR12729: Change 'llvm-objdump' to display the available targets.Pete Cooper2012-05-031-0/+3
* Remove accidentally added file.Jakob Stoklund Olesen2012-05-031-0/+0
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-033-37/+32
* Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen2012-05-032-4/+17
* Emit SuperRegMasks as part of the existing SubClassMask arrays.Jakob Stoklund Olesen2012-05-032-102/+83
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-036-44/+128
* Factor the logic for testing whether a basic block is viable for codeChandler Carruth2012-05-032-14/+29
* remove calls to calloc if the allocated memory is not used (it was already be...Nuno Lopes2012-05-033-5/+5
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-0318-93/+5036
* Add rudimentary CMake logic for detecting Graphviz.Ted Kremenek2012-05-032-1/+2
* add support for calloc to objectsize loweringNuno Lopes2012-05-034-5/+88
* Fix the type of SubClassMask.Jakob Stoklund Olesen2012-05-031-1/+1
* Compress tables for getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-19/+67
* Add the half type to the LLVM IR vim syntax highlighting.Owen Anderson2012-05-031-1/+1
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-032-4/+33
* Don't override subreg functions in targets without subregisters.Jakob Stoklund Olesen2012-05-032-44/+46
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-039-1339/+4107
* replace 'break's with 'return 0' in visitCallInst code for objectsize, since ...Nuno Lopes2012-05-031-5/+5
* Use correct variable in this example. Pointed out by waynix on IRC.Duncan Sands2012-05-031-1/+1
* Use 'unsigned' instead of 'int' in a few places dealing with counts of vector...Craig Topper2012-05-031-3/+3
* Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the ...Craig Topper2012-05-033-22/+37
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-033-17/+28
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-034-8/+45
* Whitespace cleanup.Bill Wendling2012-05-021-87/+80
* [docs] Include the Kaleidescope tutorial in the Sphinx docs build.Daniel Dunbar2012-05-0220-52/+26
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just...Owen Anderson2012-05-022-0/+27
* For Intel Atom, use ILP scheduling always, instead of ILP for 64 bitPreston Gurd2012-05-021-4/+4
* Change the Intel Atom detection code to recognizePreston Gurd2012-05-022-3/+5
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