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* Implement spill and fill of I64Regs.Jakob Stoklund Olesen2013-05-202-2/+17
* Mark i64 SETCC as expand so it is turned into a SELECT_CC.Jakob Stoklund Olesen2013-05-202-0/+12
* Replace some bit operations with simpler ones. No functionality change.Benjamin Kramer2013-05-193-12/+9
* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-194-5/+14
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-192-0/+16
* Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>Bob Wilson2013-05-191-0/+3
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-192-0/+32
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-193-27/+42
* SubArch support in MCJIT unittestRenato Golin2013-05-193-3/+31
* [Sparc] Rearrange integer registers' allocation order so that register alloca...Venkatraman Govindaraju2013-05-193-11/+24
* AArch64: enable MCJIT unittestsTim Northover2013-05-193-1/+3
* Handle i64 FrameIndex nodes in SPARC v9 mode.Jakob Stoklund Olesen2013-05-192-1/+11
* AArch64: make RuntimeDyld relocations idempotentTim Northover2013-05-191-2/+22
* Invalidate instruction cache when setting memory to be executable.Tim Northover2013-05-196-15/+7
* Temporarily disable this test because it is failing when using libc++.Bob Wilson2013-05-191-2/+3
* Move the remaining simplify-libcalls tests to instcombine, merging most of th...Benjamin Kramer2013-05-1912-138/+137
* Print uint64_t -debug text correctly on 32-bit hostsTim Northover2013-05-191-5/+5
* Unsupported remote JIT on ARMRenato Golin2013-05-189-6/+17
* isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.David Majnemer2013-05-182-0/+25
* LoopVectorize: Handle single edge PHIsArnold Schwaighofer2013-05-182-4/+26
* docs/Passes: fix some typosDmitri Gribenko2013-05-181-4/+4
* Add basic support for ELF32-ppc relocations to llvm-dwarfdump.Benjamin Kramer2013-05-182-0/+17
* Check InlineAsm clobbers in PPCCTRLoopsHal Finkel2013-05-182-0/+53
* AArch64: add CMake dependency to fix very parallel buildsTim Northover2013-05-181-0/+2
* X86: Bad peephole interaction between adc, MOV32r0David Majnemer2013-05-182-3/+45
* Remove duplicated commentMatt Arsenault2013-05-181-5/+0
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-1830-100/+122
* Support unaligned load/store on more ARM targetsJF Bastien2013-05-174-140/+193
* Fix the configure build.Rafael Espindola2013-05-171-1/+1
* Convert obj2yaml to use yamlio.Rafael Espindola2013-05-177-761/+580
* Fix the build in c++11 mode.Rafael Espindola2013-05-171-2/+2
* Replace redundant codeMatt Arsenault2013-05-171-7/+2
* Add missing -*- C++ -*- to headersMatt Arsenault2013-05-173-5/+5
* Add missing verb to comment in PassNameParser.hDerek Schuff2013-05-171-3/+3
* R600: Lower int_load_input to copyFromReg instead of Register nodeVincent Lejeune2013-05-172-1/+126
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-1719-42/+56
* R600: Use depth first scheduling algorithmVincent Lejeune2013-05-174-81/+33
* R600: Replace big texture opcode switch in scheduler by usesTC/usesVCVincent Lejeune2013-05-171-23/+3
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-1711-27/+281
* R600: Improve texture handlingVincent Lejeune2013-05-1712-217/+741
* R600: Rename 128 bit registers.Vincent Lejeune2013-05-173-26/+25
* R600: Some factorizationVincent Lejeune2013-05-175-203/+221
* R600: Factorize Fetch size limit inside AMDGPUSubTargetVincent Lejeune2013-05-174-13/+13
* R600: prettier dump of clampVincent Lejeune2013-05-172-4/+4
* R600: Fix encoding for R600 family GPUsTom Stellard2013-05-172-0/+31
* R600: Pass MCSubtargetInfo reference to R600CodeEmitterTom Stellard2013-05-173-6/+10
* [Sparc] Implements hasReservedCallFrame and hasFP.Venkatraman Govindaraju2013-05-173-1/+33
* X86: Make shuffle -> shift conversion more aggressive about undefs.Benjamin Kramer2013-05-173-20/+54
* FileCheckize test.Benjamin Kramer2013-05-171-5/+15
* LoopVectorize: Simplify code. No functionality change.Benjamin Kramer2013-05-171-21/+5