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* Bring LICM into compliance with the new "Memory Model for Concurrent ↵Eli Friedman2011-07-202-18/+67
| | | | | | Operations" in LangRef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135625 91177308-0d34-0410-b5e6-96231b3b80d8
* Commit LangRef changes for LLVM concurrency model. Start of supporting ↵Eli Friedman2011-07-201-0/+86
| | | | | | C++0x memory model and atomics. See thread on llvmdev titled "Reviving the new LLVM concurrency model". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135624 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak the MSVC build. Since the "next" function already exists in the MSVC ↵Francois Pichet2011-07-201-3/+3
| | | | | | headers, we need the explicit llvm:: qualifier to prevent a conflict. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135623 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit.Jim Grosbach2011-07-203-12/+7
| | | | | | | | Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135617 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-205-37/+35
| | | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix cmake again :)Benjamin Kramer2011-07-201-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135613 91177308-0d34-0410-b5e6-96231b3b80d8
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-2028-298/+96
| | | | | | | | There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix cmake.Benjamin Kramer2011-07-201-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135609 91177308-0d34-0410-b5e6-96231b3b80d8
* Sketch out an CFG reconstruction mode for llvm-objdump.Benjamin Kramer2011-07-203-3/+242
| | | | | | | | | | | | | - Not great yet, but it's a start. - Requires an object file with a symbol table. (I really want to fix this, but it'll need a whole new algorithm) - ELF and COFF won't work at the moment due to libObject shortcomings. To try it out run $ llvm-objdump -d --cfg foo.o This will create a graphviz file for every symbol in the object file's text section containing a CFG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135608 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.Eli Friedman2011-07-202-3/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
* Add parsing/encoding tests for ARM ORR instruction.Jim Grosbach2011-07-202-6/+79
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
* Consolidate ARM NOP encoding test.Jim Grosbach2011-07-202-11/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding tests for MVNJim Grosbach2011-07-201-0/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing of MUL instruction.Jim Grosbach2011-07-202-1/+16
| | | | | | | | Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.Eli Friedman2011-07-202-5/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135595 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize the EHFrameSection pointer to zero.Benjamin Kramer2011-07-201-0/+1
| | | | | | This should fix the spurious buildbot errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135594 91177308-0d34-0410-b5e6-96231b3b80d8
* Regenerate configure and friends for Chad.Eric Christopher2011-07-202-2/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135592 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a GCC warning.Jay Foad2011-07-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135581 91177308-0d34-0410-b5e6-96231b3b80d8
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-2054-232/+277
| | | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
* Include MCRegisterInfo to eliminate a compilation warning.Evan Cheng2011-07-201-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135575 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the CMake build.Francois Pichet2011-07-201-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135573 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-2027-840/+900
| | | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars: Added getInsertPointForUses to find a valid place to truncate the IV.Andrew Trick2011-07-202-15/+71
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135568 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-useAndrew Trick2011-07-201-54/+61
| | | | | | | | info. Holding Use* pointers is bad form even though it happened to work in this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135566 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ↵NAKAMURA Takumi2011-07-201-1/+2
| | | | | | to appease test/CodeGen/X86 on cygwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
* New pointer rotate test.Eric Christopher2011-07-201-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
* Extra semi-colon.Eric Christopher2011-07-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135561 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars test case for r135558.Andrew Trick2011-07-201-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135559 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars -disable-iv-rewrite fix: derived GEP IVsAndrew Trick2011-07-202-6/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135558 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't leak CodeGenInfos.Benjamin Kramer2011-07-201-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135555 91177308-0d34-0410-b5e6-96231b3b80d8
* Change name of class.Akira Hatanaka2011-07-201-23/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135550 91177308-0d34-0410-b5e6-96231b3b80d8
* Define classes for definitions of atomic instructions.Akira Hatanaka2011-07-201-106/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135546 91177308-0d34-0410-b5e6-96231b3b80d8
* Build and install the archive when building the Apple way.Bill Wendling2011-07-191-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135538 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-194-2/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.Evan Cheng2011-07-192-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10386: Don't try to split an edge from an indirectbr.Eli Friedman2011-07-192-2/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135534 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix off-by-one.Benjamin Kramer2011-07-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135533 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-197-50/+86
| | | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
* Distinguish between two copies of one inlined variable.Devang Patel2011-07-194-3/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135528 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing of MRS instruction.Jim Grosbach2011-07-194-10/+24
| | | | | | | | | Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance the FixedLengthDecoder to be able to generate plausible-looking ↵Owen Anderson2011-07-194-112/+140
| | | | | | decoders for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
* Change variable name.Akira Hatanaka2011-07-191-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135522 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach2011-07-193-9/+22
| | | | | | | Add range checking to the immediate operands. Update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka2011-07-192-29/+30
| | | | | | | ANDi, when the instruction does not have any immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
* Move mr[r]c[2] ARM tests and tidy up a bit.Jim Grosbach2011-07-192-10/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM testcases for MOVT.Jim Grosbach2011-07-192-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
* Use descriptive variable names. Akira Hatanaka2011-07-191-154/+177
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135514 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for MOV (register).Jim Grosbach2011-07-193-19/+46
| | | | | | | | | Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2011-07-191-12/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135507 91177308-0d34-0410-b5e6-96231b3b80d8
* Tighten conditional for 'mov' cc_out.Jim Grosbach2011-07-191-1/+2
| | | | | | | | Make sure we only clobber the cc_out operand if it is indeed a default non-setting operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8