aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-2025-109/+110
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
* First steps in ARM AsmParser support for .eabi_attribute and .archJason W Kim2011-12-201-0/+18
| | | | | | | (Both used for Linux gnueabi) No behavioral change yet (no tests need so far) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the second fix related to VZEXT_MOVL node.Elena Demikhovsky2011-12-202-1/+15
| | | | | | | | | | | | | | | | | | | | | | The failure that I see in the current version is: LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14] 0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13] 0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12] 0x18b9870: v4i64 = undef [ID=4] 0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10] 0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9970: i32 = Constant<0> [ID=3] 0x18b9170: v2i64 = undef [ORD=1] [ID=1] 0x18b9570: i32 = Constant<2> [ID=5] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin teaching the X86 target how to efficiently codegen patterns thatChandler Carruth2011-12-203-21/+49
| | | | | | | | | | | | | | | use the zero-undefined variants of CTTZ and CTLZ. These are just simple patterns for now, there is more to be done to make real world code using these constructs be optimized and codegen'ed properly on X86. The existing tests are spiffed up to check that we no longer generate unnecessary cmov instructions, and that we generate the very important 'xor' to transform bsr which counts the index of the most significant one bit to the number of leading (most significant) zero bits. Also they now check that when the variant with defined zero result is used, the cmov is still produced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes a potential compilation error.Manuel Klimek2011-12-202-13/+10
| | | | | | | Pulling the template implementation into the header to guarantee that it's visible to all possible instantiations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146973 91177308-0d34-0410-b5e6-96231b3b80d8
* Pulls the implementation of skip() into JSONParser.Manuel Klimek2011-12-202-36/+35
| | | | | | | This is the first step towards migrating more of the parser implementation into the parser class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146971 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixing option for JSON benchmark broken since the change to size_t.Manuel Klimek2011-12-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146970 91177308-0d34-0410-b5e6-96231b3b80d8
* Addressing style issues in JSON parser.Manuel Klimek2011-12-202-10/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146968 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up the CMake build for the new files added in r146960, they'reChandler Carruth2011-12-2016-0/+17
| | | | | | likely to stay either way that discussion ends up resolving itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert pragma clang suppressions that confuse GCC. (I'll worry about how to ↵David Blaikie2011-12-201-5/+0
| | | | | | suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146965 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few lines to the release notes:Nadav Rotem2011-12-201-0/+11
| | | | | | | | | 1. pointer-vector 2. type legalizer changes and vector-select 3. X86 ISA changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146964 91177308-0d34-0410-b5e6-96231b3b80d8
* Unweaken vtables as per ↵David Blaikie2011-12-20151-121/+742
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
* Unit test for r146950: LSR postinc expansion, PR11571.Andrew Trick2011-12-201-0/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146951 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR: Fix another corner case in expansion of postinc users.Andrew Trick2011-12-201-0/+14
| | | | | | | Fixes PR11571: Instruction does not dominate all uses git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146950 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson2011-12-202-2/+60
| | | | | | | | | | | | We used to rely on the *eh_sjlj_setjmp instructions to mark that a function with setjmp/longjmp exception handling clobbers all the registers. But with the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are expanded away earlier, before PEI can see them to determine what registers to save and restore. Mark the dispatchsetup instruction in the same way, since that instruction cannot be expanded early. This also more accurately reflects when the registers are clobbered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typoChris Lattner2011-12-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146940 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a line to ReleaseNotes for half float.Dan Gohman2011-12-201-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146939 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach2011-12-202-0/+34
| | | | | | | | | | "mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that PR11464 is fixed, reapply the patch to fix PR11464, Chris Lattner2011-12-202-0/+35
| | | | | | | | | | merging types by name when we can. We still don't guarantee type name linkage but we do it when obviously the right thing to do. This makes LTO type names easier to read, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146932 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR11464 by preventing the linker from mapping two different struct types ↵Chris Lattner2011-12-202-12/+46
| | | | | | from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146929 91177308-0d34-0410-b5e6-96231b3b80d8
* add a method to improve compatibility with SmallVector.Chris Lattner2011-12-201-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146928 91177308-0d34-0410-b5e6-96231b3b80d8
* Add basic generic CodeGen support for half.Dan Gohman2011-12-208-81/+118
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.Jim Grosbach2011-12-192-0/+45
| | | | | | | | e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117" rdar://10603913 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
* Move tests to FileCheck.Evan Cheng2011-12-192-3/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146923 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-196-4/+78
| | | | | | rdar://9932658 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a if-conversion optimization that allows 'true' side of a diamond to beEvan Cheng2011-12-192-5/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914 91177308-0d34-0410-b5e6-96231b3b80d8
* Add "using" to silence warnings.Eli Friedman2011-12-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146913 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for r146900.Akira Hatanaka2011-12-191-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146901 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for matching immediates whose lower 16-bit is cleared. TheseAkira Hatanaka2011-12-194-6/+21
| | | | | | | | patterns emit a single LUi instruction instead of a pair of LUi and ORi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to fix PR11607 by shuffling around which class defines which methods.Eli Friedman2011-12-192-7/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146897 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-1910-132/+117
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON two-operand aliases for VPADD.Jim Grosbach2011-12-192-0/+20
| | | | | | rdar://10602276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove definitions of double word shift plus 32 instructions. Assembler orAkira Hatanaka2011-12-193-27/+15
| | | | | | | | | direct-object emitter should emit the appropriate shift instruction depending on the shift amount. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP pre-UAL mnemonic aliases for fmul[sd].Jim Grosbach2011-12-192-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused predicate.Akira Hatanaka2011-12-191-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146889 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-192-4/+2
| | | | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].Jim Grosbach2011-12-192-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON implied destination aliases for VMAX/VMIN.Jim Grosbach2011-12-193-110/+304
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach2011-12-194-17/+19
| | | | | | | There's more variation that we need to handle. Error checking will need to be on operand predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2011-12-191-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a register class that can just as well be synthesized.Jakob Stoklund Olesen2011-12-192-9/+4
| | | | | | | Add the new TableGen register class synthesizer feature to the release notes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle sub-register operands in recomputeRegClass().Jakob Stoklund Olesen2011-12-191-4/+6
| | | | | | | | | | | Now that getMatchingSuperRegClass() returns accurate results, it can be used to compute constraints imposed by instructions using a sub-register of a virtual register. This means we can recompute the register class of any virtual register by combining the constraints from all its uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146874 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-198-231/+90
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
* Synthesize register classes for TRI::getMatchingSuperRegClass().Jakob Stoklund Olesen2011-12-192-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Teach TableGen to create the missing register classes needed for getMatchingSuperRegClass() to return maximal results. The function is still not auto-generated, so it still returns inexact results. This produces these new register classes: ARM: QQPR_with_dsub_0_in_DPR_8 QQQQPR_with_dsub_0_in_DPR_8 X86: GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP GR64_with_sub_16bit_in_GR16_NOREX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_with_sub_32bit_in_GR32_TC GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC GR64_with_sub_32bit_in_GR32_AD GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX The other targets in the tree are not weird enough to be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow for benchmarking more than 4GB of memoryManuel Klimek2011-12-191-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146864 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds a flag to allow specifying the memory limitations of the JSON benchmark.Manuel Klimek2011-12-191-7/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146863 91177308-0d34-0410-b5e6-96231b3b80d8
* - Use getExitingBlock instead of getExitingBlocks.Jakub Staszak2011-12-181-13/+11
| | | | | | | - Remove trailing spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146854 91177308-0d34-0410-b5e6-96231b3b80d8
* Another variadics tweak.Benjamin Kramer2011-12-181-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger2011-12-186-22/+70
| | | | | | | attribute themselve. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146851 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the fancy new VariadicFunction template instead of a plain variadic ↵Benjamin Kramer2011-12-181-34/+33
| | | | | | | | function. Some compilers were complaining about passing StringRef to it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2024-09-12 09:44:52 +0000