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* [Support/StringRef] Add find_last_not_of and {r,l,}trim.Michael J. Spencer2012-05-113-0/+76
* Remove extraneous ; and the resulting warning.Bill Wendling2012-05-111-1/+1
* Add mention of Glasgow Haskell Compiler.Bill Wendling2012-05-111-1/+34
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-112-0/+16
* Updated instruction table due to addded intrinsics.Brendon Cahoon2012-05-111-1880/+1943
* Remove warnings from HexagonVLIWPacketizer.Sirish Pande2012-05-111-3/+3
* Some release notes for dragonegg.Duncan Sands2012-05-111-6/+19
* Hexagon constant extender support.Brendon Cahoon2012-05-1117-343/+3700
* Typo.Chad Rosier2012-05-111-1/+1
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Min...Chad Rosier2012-05-112-13/+3
* Hexagon V5 intrinsics support.Sirish Pande2012-05-114-961/+2613
* Defer computation of SuperRegs.Jakob Stoklund Olesen2012-05-112-11/+36
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-112-4/+38
* objectsize: add a few more tests and fix a bugNuno Lopes2012-05-112-1/+56
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-114-130/+350
* PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to i...Stepan Dyatkovskiy2012-05-112-1/+1
* Fix test/CodeGen/X86/tls-pie.ll.Hans Wennborg2012-05-111-1/+1
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-115-20/+48
* Added the missing bit definition for the 4th bit of the STR (post reg) instru...Silviu Baranga2012-05-114-0/+72
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate o...Silviu Baranga2012-05-113-3/+12
* Fix a use after free when the streamer is destroyed. Fixes pr12622.Rafael Espindola2012-05-111-1/+1
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-1112-35/+35
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-118-55/+55
* Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman2012-05-112-1/+16
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-113-27/+162
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-118-2/+55
* Allow unique_file to take a mode for file permissions, but defaultEric Christopher2012-05-113-7/+10
* Fix intendation.Chad Rosier2012-05-101-1/+1
* Compute secondary sub-registers.Jakob Stoklund Olesen2012-05-102-3/+161
* objectsize: add support for GEPs with non-constant indexesNuno Lopes2012-05-104-34/+59
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-102-4/+31
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
* misched: Introducing Top and Bottom register pressure trackers during schedul...Andrew Trick2012-05-103-39/+112
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
* Hexagon V5 FP Support.Sirish Pande2012-05-1029-194/+862
* RegPressure: API for speculatively checking instruction pressure.Andrew Trick2012-05-102-1/+229
* RegPressure: fix array index iteration style.Andrew Trick2012-05-101-8/+8
* Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.Dan Gohman2012-05-104-3/+68
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-103-161/+27
* Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen2012-05-102-19/+38
* Rewrite ScalarEvolution::hasOperand to use an explicit worklist insteadDan Gohman2012-05-101-35/+50
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