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* TBAA: update tbaa format from scalar format to struct-path aware format.Manman Ren2013-09-309-63/+74
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191690 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases when they are not needed.Manman Ren2013-09-3020-207/+131
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191689 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-303-28/+75
| | | | | | | | | | This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-303-49/+202
| | | | | | | | | | This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Clean up ARMAsmParser::validateInstruction().Tilmann Scheller2013-09-301-38/+36
| | | | | | | | | Fix some LLVM Coding Standards violations. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191686 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-303-16/+57
| | | | | | | | | | This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191685 91177308-0d34-0410-b5e6-96231b3b80d8
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-303-15/+41
| | | | | | | | | and not an MSA register Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Use FileCheck instead of grep for ARM LDRD negative tests.Tilmann Scheller2013-09-301-19/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
* Move command line options to the users of libLTO. Fixes --enable-shared build.Rafael Espindola2013-09-306-176/+185
| | | | | | Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191680 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Enable building LTO on WIN32."Rafael Espindola2013-09-304-16/+5
| | | | | | | | | | This reverts commit r191670. It was causing build failures on the msvc bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191679 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be ↵Tilmann Scheller2013-09-302-4/+25
| | | | | | | | | | | | different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678 91177308-0d34-0410-b5e6-96231b3b80d8
* Swift model: Fix uop description on some writesArnold Schwaighofer2013-09-301-2/+11
| | | | | | Those writes really need two/three uops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191677 91177308-0d34-0410-b5e6-96231b3b80d8
* BoundsChecking: Fix refacto.Benjamin Kramer2013-09-301-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191676 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert manual insert point restores to the new RAII object.Benjamin Kramer2013-09-305-62/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191675 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Replace manual fast math flag copying with the new IRBuilder ↵Benjamin Kramer2013-09-301-22/+20
| | | | | | | | | RAII helper. Defines away the issue where cast<Instruction> would fail because constant folding happened. Also slightly cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191674 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Add RAII objects to reset insertion points or fast math flags.Benjamin Kramer2013-09-304-22/+86
| | | | | | | | Inspired by the object from the SLPVectorizer. This found a minor bug in the debug loc restoration in the vectorizer where the location of a following instruction was attached instead of the location from the original instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191673 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Move fast math flags to IRBuilderBase.Benjamin Kramer2013-09-301-34/+28
| | | | | | They don't depend on the templated stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191672 91177308-0d34-0410-b5e6-96231b3b80d8
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-309-10/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable building LTO on WIN32.Rafael Espindola2013-09-304-5/+16
| | | | | | | | | Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with MSVC and Mingw as well as re-enabling the associated test. Patch by Greg Bedwell! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191670 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in InstCombine where it attempted to cast a Value* to an Instruction*Joey Gouly2013-09-302-2/+25
| | | | | | | | | | when it was actually a Constant*. There are quite a few other casts to Instruction that might have the same problem, but this is the only one I have a test case for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191668 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Assembler: Add more negative tests for ARM LDRD.Tilmann Scheller2013-09-301-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191664 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Revert r191661: Add definitions of LFH and STFHRichard Sandiford2013-09-305-134/+0
| | | | | | | | | For some reason, adding definitions for these load and store instructions changed whether some of the build bots matched comparisons as signed or unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191663 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add definitions of LFH and STFHRichard Sandiford2013-09-305-0/+134
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191661 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford2013-09-306-14/+38
| | | | | | | | | | The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rename subregs and add subreg_h32Richard Sandiford2013-09-309-60/+61
| | | | | | | | | | | | | | Use subreg_hNN and subreg_lNN for the high and low NN bits of a register. List the low registers first, so that subreg_l32 also means the low 32 bits of a 128-bit register. Floats are stored in the upper 32 bits of a 64-bit register, so they should use subreg_h32 rather than subreg_l32. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix a broken link to mips.com in the documentation.Daniel Sanders2013-09-301-1/+1
| | | | | | | It now points to the equivalent page on imgtec.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191658 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add change missing from previous commitRichard Sandiford2013-09-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191656 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rename 32-bit GPR registersRichard Sandiford2013-09-306-20/+20
| | | | | | | | | I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
* Filter out repeated sections from the X86 disassembler modRMTable. Saves ↵Craig Topper2013-09-302-87/+67
| | | | | | about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191652 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few more FMA4 disassembler test cases to match the scalar set with ↵Craig Topper2013-09-301-0/+12
| | | | | | regards to combinations of L and W-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191650 91177308-0d34-0410-b5e6-96231b3b80d8
* Various x86 disassembler fixes.Craig Topper2013-09-305-53/+66
| | | | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649 91177308-0d34-0410-b5e6-96231b3b80d8
* ObjectSizeOffsetEvaluator: Don't run into infinite recursion if we have a ↵Benjamin Kramer2013-09-292-5/+24
| | | | | | | | cyclic GEP. Those can occur in dead code. PR17402. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191644 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an old workaround for a compiler that EOL'd years ago.Benjamin Kramer2013-09-291-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191643 91177308-0d34-0410-b5e6-96231b3b80d8
* Plug a memory leak in a unit test. Stack allocation is sufficient here.Benjamin Kramer2013-09-291-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191638 91177308-0d34-0410-b5e6-96231b3b80d8
* Deallocate type units when destroying a DWARFContext.Benjamin Kramer2013-09-291-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191637 91177308-0d34-0410-b5e6-96231b3b80d8
* Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.Benjamin Kramer2013-09-292-12/+17
| | | | | | | SDNode destructors are never called. As an optimization use AtomicSDNode's internal storage if we have a small number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191636 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert accidental commit.Craig Topper2013-09-291-1/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191633 91177308-0d34-0410-b5e6-96231b3b80d8
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-293-55/+9
| | | | | | cases from switch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191632 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments for XOPA map introduced with TBM instructions.aCraig Topper2013-09-292-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191630 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test that large offsets on GEPs on 32 bits targets are handled correctly.Benjamin Kramer2013-09-281-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191628 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable libcxx as part of the top level CMake build when it is checkedChandler Carruth2013-09-281-2/+3
| | | | | | | out in projects. This appears to be working on my system, and I will be watching build bots to see if there are any issues on other platforms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191624 91177308-0d34-0410-b5e6-96231b3b80d8
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-2815-21/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-289-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Silence unused variable warning on release buildsTom Stellard2013-09-281-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191604 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-2810-105/+127
| | | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-282-17/+49
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191602 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-285-94/+91
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Clean up LegalizeSetCCCondCode() functionTom Stellard2013-09-281-26/+51
| | | | | | | | | | | | | | Interpreting the results of this function is not very intuitive, so I cleaned it up to make it more clear whether or not a SETCC op was legalized and how it was legalized (either by swapping LHS and RHS or replacing with AND/OR). This patch does change functionality in the LHS and RHS swapping case, but unfortunately there are no in-tree tests for this. However, this patch is a prerequisite for R600 to take advantage of the LHS and RHS swapping, so tests will be added in subsequent commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191600 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>NAKAMURA Takumi2013-09-281-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191597 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoMatt Arsenault2013-09-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191595 91177308-0d34-0410-b5e6-96231b3b80d8
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