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* Keep global nodes in each DS Graph (by forcing them to be marked live).Vikram S. Adve2002-11-251-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4831 91177308-0d34-0410-b5e6-96231b3b80d8
* Oops. Got the MOVrm and MOVmr mixed up. Fixed. We can now print outMisha Brukman2002-11-221-2/+2
| | | | | | | instructions correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4830 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable the register allocator pass.Misha Brukman2002-11-221-1/+5
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* A simple (spilling) register allocator.Misha Brukman2002-11-221-0/+219
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* Added methods to read/write values to stack in .h, fixed implementation inMisha Brukman2002-11-222-21/+39
| | | | | | | .cpp to return the iterator correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4827 91177308-0d34-0410-b5e6-96231b3b80d8
* Added -*- C++ -*- mode to the comments.Misha Brukman2002-11-221-1/+1
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* Add a simple way to add memory locations of format [reg+offset]Misha Brukman2002-11-221-0/+9
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* Added virtual functions for storing and retrieving values from the stack.Misha Brukman2002-11-221-9/+14
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* Instead of checking op.getType() against MO_VirtualRegister andMisha Brukman2002-11-221-0/+14
| | | | | | | | | | | MO_MachineRegister, we no longer distinguish Virtual vs. Machine registers externally, they're ALL registers, all equal. Registers are only differentiated whether they are >= MRegisterInfo::FirstVirtual or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4823 91177308-0d34-0410-b5e6-96231b3b80d8
* Set SSARegMap to NULL after deleting it.Misha Brukman2002-11-221-1/+4
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* lib/Target/X86/InstSelectSimple.cpp: Add visitCallInst, visitCastInst.Brian Gaeke2002-11-222-0/+28
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* Make testcase more interestingChris Lattner2002-11-211-0/+3
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* Handle cmp Reg, 0 correctlyChris Lattner2002-11-212-20/+26
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* Printing support for more stuffChris Lattner2002-11-211-20/+20
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* Don't add implicit operandsChris Lattner2002-11-212-10/+10
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* Fix off by one bugChris Lattner2002-11-212-2/+2
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* Add fixmeChris Lattner2002-11-211-0/+3
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* Minor code cleanupsChris Lattner2002-11-212-4/+2
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* Implement printing of store instructionsChris Lattner2002-11-212-10/+40
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* The big change here is to handle printing/emission of X86II::MRMSrcMemChris Lattner2002-11-212-46/+368
| | | | | | | | instructions. Right now the only users are load instructions, and Misha's spill code git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4812 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove implicit information from instruction selectorChris Lattner2002-11-212-12/+4
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* Add printing information for MUL and DIVChris Lattner2002-11-211-12/+15
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* Fix a bug that prevented compilation of multiple functionsChris Lattner2002-11-212-0/+2
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* Move testChris Lattner2002-11-211-0/+0
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* Shuffle testcases aroundChris Lattner2002-11-214-16/+0
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* New testcaseChris Lattner2002-11-211-0/+13
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* Remove opcode information for instructions that are completely defined nowChris Lattner2002-11-211-22/+22
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* Add printing support for sahf & setccChris Lattner2002-11-211-15/+15
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* Add printing support for /0 /1 type instructionsChris Lattner2002-11-212-2/+88
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* Add support for /0 /1, etc type instructionsChris Lattner2002-11-211-5/+16
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* User defined operators are not supposed to live beyond the lifetime of theChris Lattner2002-11-211-0/+9
| | | | | | | pass. Detect and flag them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4801 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the SetCC X86 instructions to reflect the fact that they are theChris Lattner2002-11-213-14/+14
| | | | | | | register versions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4800 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify setcc code a bitChris Lattner2002-11-212-246/+122
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* Support Registers of the form (B8+ rd) for exampleChris Lattner2002-11-212-20/+110
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* Dont' set flagsChris Lattner2002-11-212-16/+10
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* Implement printing more, implement opcode output moreChris Lattner2002-11-212-20/+114
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* Huge diff do to reindeinting comments.Chris Lattner2002-11-211-85/+88
| | | | | | | Basically just adds OpSize flags for instructions that need them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4795 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new prefix flagChris Lattner2002-11-211-0/+5
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* Print another class of instructions correctly, giving us: xorl EDX, EDXChris Lattner2002-11-212-30/+74
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* Booleans are types too. And they get stored in bytes. And InstructionSelectionMisha Brukman2002-11-211-0/+1
| | | | | | | doesn't assert fail. And everyone's happy. Yay! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4792 91177308-0d34-0410-b5e6-96231b3b80d8
* Checkin testcases for bugpointChris Lattner2002-11-203-0/+37
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* Build bugpointChris Lattner2002-11-201-1/+1
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* Initial checkin of bugpointChris Lattner2002-11-208-0/+619
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* Initial checkin of Module cloning support stuffChris Lattner2002-11-204-4/+179
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* Cloning stuff doesn't modify the source moduleChris Lattner2002-11-201-1/+1
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* X86 target builds fine nowChris Lattner2002-11-201-1/+1
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* Fix symbol table problemChris Lattner2002-11-201-11/+10
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* Add definitions for function headers from MRegisterInfo.h:Misha Brukman2002-11-203-0/+188
| | | | | | | | | Some functions are in X86RegisterInfo.cpp, others, because of the data they need, are in X86RegisterClasses.cpp, which also defines some register classes: byte, short, and int. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4784 91177308-0d34-0410-b5e6-96231b3b80d8
* Check not only for MO_VirtualRegister, but MO_MachineRegister as well whenMisha Brukman2002-11-202-14/+28
| | | | | | | printing out assembly. After all, we want the real thing too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4783 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize the SSARegMap.Misha Brukman2002-11-201-0/+1
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