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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-2/+0
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-3/+20
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-6/+7
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-0/+37
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-0/+5
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-1/+3
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Add addrspacecast instruction.Matt Arsenault2013-11-151-0/+4
| | | | | | Patch by Michele Scandale! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-0/+6
| | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ISD::FROUND for libm round()Hal Finkel2013-08-071-2/+2
| | | | | | | | | | | | | | | All libm floating-point rounding functions, except for round(), had their own ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm adding ISD::FROUND so that round() can be custom lowered as well. For the most part, this is straightforward. I've added an intrinsic and a matching ISD node just like those for nearbyint() and friends. The SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed fround). This will be used by the PowerPC backend in a follow-up commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-1/+1
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-12/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+12
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-12/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-201-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10475Michael Liao2013-03-011-2/+4
| | | | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+3
| | | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-271-1/+1
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-0/+4
| | | | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-071-0/+5
| | | | | | | This adds support for TargetIndex operands during isel. The meaning of these (index, offset, flags) operands is entirely defined by the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161453 91177308-0d34-0410-b5e6-96231b3b80d8
* Doxygenify the comments of ISD nodes.Nadav Rotem2012-07-231-292/+293
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160623 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo. Patch by Cameron McInally <cameron.mcinally@nyu.edu>.Chad Rosier2012-06-191-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158754 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman2012-05-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-111-0/+3
| | | | | | | but it generates int3 on x86 instead of ud2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-181-1/+1
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148436 91177308-0d34-0410-b5e6-96231b3b80d8
* Document the fact that the selection dag changes the vselect condition typeNadav Rotem2012-01-181-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148411 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead llvm.eh.sjlj.dispatchsetup intrinsic.Bill Wendling2011-11-281-7/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145263 91177308-0d34-0410-b5e6-96231b3b80d8
* Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling2011-10-071-1/+1
| | | | | | | do. This will be useful later on with the new SJLJ stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-8/+8
| | | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the init.trampoline intrinsic, which currently combines GCC'sDuncan Sands2011-09-061-8/+13
| | | | | | | | | | | | | | | | | | | | | init.trampoline and adjust.trampoline intrinsics, into two intrinsics like in GCC. While having one combined intrinsic is tempting, it is not natural because typically the trampoline initialization needs to be done in one function, and the result of adjust trampoline is needed in a different (nested) function. To get around this llvm-gcc hacks the nested function lowering code to insert an additional parent variable holding the adjust.trampoline result that can be accessed from the child function. Dragonegg doesn't have the luxury of tweaking GCC code, so it stored the result of adjust.trampoline in the memory GCC set aside for the trampoline itself (this is always available in the child function), and set up some new memory (using an alloca) to hold the trampoline. Unfortunately this breaks Go which allocates trampoline memory on the heap and wants to use it even after the parent has exited (!). Rather than doing even more hacks to get Go working, it seemed best to just use two intrinsics like in GCC. Patch mostly by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
* Basic x86 code generation for atomic load and store instructions.Eli Friedman2011-08-241-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-1/+1
| | | | | | is to use this for architectures that have a native FMA instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-1/+2
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment.Bill Wendling2011-05-111-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131173 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* fix thinko :)Chris Lattner2011-02-131-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125466 91177308-0d34-0410-b5e6-96231b3b80d8
* Revisit my fix for PR9028: the issue is that DAGCombine was Chris Lattner2011-02-131-6/+14
| | | | | | | | | | generating i8 shift amounts for things like i1024 types. Add an assert in getNode to prevent this from occuring in the future, fix the buggy transformation, revert my previous patch, and document this gotcha in ISDOpcodes.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125465 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-261-0/+8
| | | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
| | | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment. INLINEASM node operand #3 is IsAlignStack bit.Evan Cheng2011-01-071-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123036 91177308-0d34-0410-b5e6-96231b3b80d8
* Change EXTRACT_SUBVECTOR to require a constant index.Bob Wilson2011-01-071-2/+2
| | | | | | | | We were never generating any of these nodes with variable indices, and there was one legalizer function asserting on a non-constant index. If we ever have a need to support variable indices, we can add this back again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122993 91177308-0d34-0410-b5e6-96231b3b80d8
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
* Spelling typo fix. s/incput/input/. Thanks, Bob!Jim Grosbach2010-10-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116880 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-0/+7
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the first step towards refactoring the x86 vector shuffle code. TheBruno Cardoso Lopes2010-08-201-1/+1
| | | | | | | | | | | | | | general idea here is to have a group of x86 target specific nodes which are going to be selected during lowering and then directly matched in isel. The commit includes the addition of those specific nodes and a *bunch* of patterns, and incrementally we're going to switch between them and what we have right now. Both the patterns and target specific nodes can change as we move forward with this work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comment to remove special case for vector extending loads. AnBob Wilson2010-08-191-5/+2
| | | | | | | | extending vector load should extend each element in the same way as the corresponding scalar extending load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111577 91177308-0d34-0410-b5e6-96231b3b80d8
* When splitting a VAARG, remember its alignment.Rafael Espindola2010-06-261-2/+3
| | | | | | This produces terrible but correct code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106952 91177308-0d34-0410-b5e6-96231b3b80d8
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