| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update aosp/master llvm for rebase to r233350 | Pirama Arumuga Nainar | 2015-04-09 | 1 | -6/+0 |
| * | Update aosp/master LLVM for rebase to r230699. | Stephen Hines | 2015-03-23 | 1 | -0/+6 |
| * | Update LLVM for 3.5 rebase (r209712). | Stephen Hines | 2014-05-29 | 1 | -34/+37 |
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -4/+15 |
| * | Explicitly request unsigned enum types when desired | Reid Kleckner | 2013-10-08 | 1 | -1/+1 |
| * | Use SmallVectorImpl::iterator/const_iterator instead of SmallVector | Eric Christopher | 2013-07-03 | 1 | -4/+4 |
| * | Machine Model: Add MicroOpBufferSize and resource BufferSize. | Andrew Trick | 2013-06-15 | 1 | -21/+2 |
| * | MI Sched: eliminate local vreg copies. | Andrew Trick | 2013-04-24 | 1 | -3/+2 |
| * | MI-Sched: schedule physreg copies. | Andrew Trick | 2013-04-13 | 1 | -12/+13 |
| * | Fix incorrect ScheduleDAG comment and formalize Weak edges. | Andrew Trick | 2013-03-01 | 1 | -2/+12 |
| * | Fix #includes, so we include only what we really need. | Jakub Staszak | 2013-02-20 | 1 | -2/+1 |
| * | MachineScheduler support for viewGraph. | Andrew Trick | 2013-01-25 | 1 | -2/+2 |
| * | ScheduleDAG: Added isBoundaryNode to conveniently detect a common corner case. | Andrew Trick | 2013-01-25 | 1 | -1/+12 |
| * | MIsched: Added biasCriticalPath. | Andrew Trick | 2013-01-24 | 1 | -0/+4 |
| * | Sort the #include lines for the include/... tree with the script. | Chandler Carruth | 2012-12-03 | 1 | -4/+4 |
| * | misched: Don't consider artificial edges weak edges. | Andrew Trick | 2012-11-13 | 1 | -2/+1 |
| * | misched: Infrastructure for weak DAG edges. | Andrew Trick | 2012-11-12 | 1 | -21/+40 |
| * | misched: TargetSchedule interface for machine resources. | Andrew Trick | 2012-11-06 | 1 | -3/+6 |
| * | ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies. | Andrew Trick | 2012-11-06 | 1 | -34/+29 |
| * | misched: Use the TargetSchedModel interface wherever possible. | Andrew Trick | 2012-10-10 | 1 | -5/+0 |
| * | misched: remove forceUnitLatencies. Defaults are handled by the default Sched... | Andrew Trick | 2012-10-08 | 1 | -5/+0 |
| * | Simplify the computeOperandLatency API. | Andrew Trick | 2012-08-23 | 1 | -2/+17 |
| * | sched: Avoid trivially redundant DAG edges. Take the one with higher latency. | Andrew Trick | 2012-06-13 | 1 | -2/+7 |
| * | misched: API for minimum vs. expected latency. | Andrew Trick | 2012-06-05 | 1 | -9/+6 |
| * | misched: implemented a framework for top-down or bottom-up scheduling. | Andrew Trick | 2012-03-14 | 1 | -0/+7 |
| * | misched preparation: rename core scheduler methods for consistency. | Andrew Trick | 2012-03-07 | 1 | -6/+6 |
| * | misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. | Andrew Trick | 2012-03-07 | 1 | -13/+3 |
| * | misched preparation: modularize schedule emission. | Andrew Trick | 2012-03-07 | 1 | -11/+0 |
| * | misched preparation: modularize schedule printing. | Andrew Trick | 2012-03-07 | 1 | -2/+0 |
| * | misched preparation: modularize schedule verification. | Andrew Trick | 2012-03-07 | 1 | -3/+3 |
| * | Cleanup in preparation for misched: Move DAG visualization logic. | Andrew Trick | 2012-03-07 | 1 | -0/+4 |
| * | Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ... | Andrew Trick | 2012-03-07 | 1 | -5/+0 |
| * | misched comments | Andrew Trick | 2012-03-07 | 1 | -1/+2 |
| * | Initialize SUnits before DAG building. | Andrew Trick | 2012-02-22 | 1 | -0/+1 |
| * | Move some llvm_unreachable's from r149849 out of switch statements to satisfy... | Craig Topper | 2012-02-06 | 1 | -1/+1 |
| * | Convert assert(0) to llvm_unreachable | Craig Topper | 2012-02-05 | 1 | -2/+1 |
| * | Move Sched::Preference out of TargetMachine.h where it is not referenced. | Evan Cheng | 2012-01-12 | 1 | -1/+1 |
| * | Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_... | David Blaikie | 2011-12-20 | 1 | -0/+1 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -5/+5 |
| * | Added -stress-sched flag in the Asserts build. | Andrew Trick | 2011-06-15 | 1 | -0/+6 |
| * | Remove dead code. | Devang Patel | 2011-06-02 | 1 | -1/+0 |
| * | Be careful about scheduling nodes above previous calls. It increase usages of | Evan Cheng | 2011-04-26 | 1 | -3/+4 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -2/+2 |
| * | In the pre-RA scheduler, maintain cmp+br proximity. | Andrew Trick | 2011-04-14 | 1 | -3/+4 |
| * | Added a check in the preRA scheduler for potential interference on a | Andrew Trick | 2011-04-07 | 1 | -6/+7 |
| * | Typos. | Eric Christopher | 2011-03-07 | 1 | -2/+2 |
| * | Introducing a new method of tracking register pressure. We can't | Andrew Trick | 2011-02-04 | 1 | -4/+7 |
| * | Header warning patrol. | Eric Christopher | 2010-12-25 | 1 | -2/+2 |
| * | Minor cleanup related to my latest scheduler changes. | Andrew Trick | 2010-12-24 | 1 | -1/+1 |
| * | Various bits of framework needed for precise machine-level selection | Andrew Trick | 2010-12-24 | 1 | -1/+29 |
