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* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-2/+2
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
* Matrix simplification in PBQP may push infinite costs onto register options.Lang Hames2012-04-031-0/+6
| | | | | | | | | The colorability heuristic should count these as denied registers. No test case - this exposed a bug on an out-of-tree target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153958 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes to r153903. Added missing explanation of behaviour when the ↵Pete Cooper2012-04-031-0/+5
| | | | | | VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153914 91177308-0d34-0410-b5e6-96231b3b80d8
* Moved LiveRangeEdit.h so that it can be called from other parts of the ↵Pete Cooper2012-04-021-0/+202
| | | | | | backend, not just libCodeGen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153906 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-011-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola2012-03-314-4/+14
| | | | | | | | This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable machine code verification in the entire code generator.Jakob Stoklund Olesen2012-03-281-5/+0
| | | | | | | | | | Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen2012-03-271-0/+22
| | | | | | | | | | | | | | | | | | | | Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153511 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a debug option to dump PBQP graphs during register allocation.Lang Hames2012-03-261-0/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153483 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer2012-03-171-1/+12
| | | | | | This is particularly helpful as both arguments tend to be constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152991 91177308-0d34-0410-b5e6-96231b3b80d8
* Limit the number of memory operands in MachineInstr to 2^16 and store the ↵Benjamin Kramer2012-03-161-6/+7
| | | | | | | | number in padding. Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152930 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." ↵NAKAMURA Takumi2012-03-161-2/+1
| | | | | | | | | for workaround of g++-4.4's miscompilation. It caused MSP430DAGToDAGISel::SelectIndexedBinOp() to be miscompiled. When two ReplaceUses()'s are expanded as inline, vtable in base class is stored to latter (ISelUpdater)ISU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152877 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-141-0/+7
| | | | | | | | | | | | | | | | | | | New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152700 91177308-0d34-0410-b5e6-96231b3b80d8
* s/SjLjEHPass/SjLjEHPrepare/Bill Wendling2012-03-131-2/+2
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152658 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline the d'tor and add an anchor instead.Bill Wendling2012-03-131-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152613 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-6/+6
| | | | | | uint16_t to reduce space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick2012-03-091-5/+5
| | | | | | not private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: allow the default scheduler to be one chosen by the target.Andrew Trick2012-03-091-3/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8
* Added TargetPassConfig::enablePassAndrew Trick2012-03-091-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152359 91177308-0d34-0410-b5e6-96231b3b80d8
* misched interface: Expose the MachineScheduler pass.Andrew Trick2012-03-081-0/+86
| | | | | | | | Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.Andrew Trick2012-03-072-13/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152262 91177308-0d34-0410-b5e6-96231b3b80d8
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-071-0/+339
| | | | | | implement their own MachineScheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-073-11/+11
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-13/+3
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
* misched preparation: modularize schedule emission.Andrew Trick2012-03-071-11/+0
| | | | | | ScheduleDAG has nothing to do with how the instructions are scheduled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-2/+0
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-3/+3
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-071-0/+4
| | | | | | Soon, ScheduleDAG will not refer to the BB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MachineBasicBlock::getFullName() to standardize/factor codegen ↵Andrew Trick2012-03-071-0/+4
| | | | | | diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152176 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick2012-03-071-5/+0
| | | | | | the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
* misched commentsAndrew Trick2012-03-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an unused function.Nadav Rotem2012-03-051-13/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152028 91177308-0d34-0410-b5e6-96231b3b80d8
* Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen2012-03-041-0/+1
| | | | | | | | | | | MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152008 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
* delete dead code, patch by Michael Spencer.Jia Liu2012-03-021-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151909 91177308-0d34-0410-b5e6-96231b3b80d8
* Make InlineSpiller bundle-aware.Jakob Stoklund Olesen2012-03-011-0/+9
| | | | | | | | | | Simply treat bundles as instructions. Spill code is inserted between bundles, never inside a bundle. Rewrite all operands in a bundle at once. Don't attempt and memory operand folding inside bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151787 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getBundleStart() into MachineInstrBundle.h.Jakob Stoklund Olesen2012-03-013-11/+19
| | | | | | | | | This allows the function to be inlined, and makes it suitable for use in getInstructionIndex(). Also provide a const version. C++ is great for touch typing practice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151782 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an analyzeVirtReg() function.Jakob Stoklund Olesen2012-02-291-0/+33
| | | | | | | | | | | | | | This function does more or less the same as MI::readsWritesVirtualRegister(), but it supports bundles as well. It also determines if any constraint requires reading and writing operands to use the same register. Most clients want to know. Use the more modern MO.readsReg() instead of trying to sort out undefs and partial redefines. Stop supporting the extra full <imp-def> operand as an alternative to <def,undef> sub-register defines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151690 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the operand iterator into MachineInstrBundle.h where it belongs.Jakob Stoklund Olesen2012-02-292-67/+108
| | | | | | | | | Extract a base class and provide four specific sub-classes for iterating over const/non-const bundles/instructions. This eliminates the mystery bool constructor argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151684 91177308-0d34-0410-b5e6-96231b3b80d8
* Instructions inside a bundle have the same number as the bundle itself.Jakob Stoklund Olesen2012-02-281-2/+6
| | | | | | | | | | SlotIndexes are not assigned to instructions inside bundles, but it is still valid to look up the index of those instructions. The reverse getInstructionFromIndex() will return the first instruction in the bundle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151672 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MachineOperand iterator class.Jakob Stoklund Olesen2012-02-271-0/+67
| | | | | | | | The MIOperands iterator can visit operands on a single instruction, or all operands in a bundle. This simplifies code like the register allocator that treats bundles as a set of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151529 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace a DenseSet with SmallPtrSet.Benjamin Kramer2012-02-231-6/+4
| | | | | | SmallSet of pointer is the same as SmallPtrSet, use the latter directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151281 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip a layer of boilerplate from the VLIWPacketizer by storing the ↵Benjamin Kramer2012-02-231-2/+1
| | | | | | scheduler as an opaque pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151252 91177308-0d34-0410-b5e6-96231b3b80d8
* Track reserved registers separately from RegsAvailable.Jakob Stoklund Olesen2012-02-231-2/+3
| | | | | | | The bulk masking operations from register mask operands don't account for reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151222 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the use of an alternate symbol for calculating a function's size.Hal Finkel2012-02-221-0/+5
| | | | | | | | | | | | | The standard function epilog includes a .size directive, but ppc64 uses an alternate local symbol to tag the actual start of each function. Until recently, binutils accepted the .size directive as: .size test1, .Ltmp0-test1 however, using this directive with recent binutils will result in the error: .size expression for XXX does not evaluate to a constant so we must use the label which actually tags the start of the function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151200 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer2012-02-222-9/+16
| | | | | | Patch by Joe Groff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151183 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize SUnits before DAG building.Andrew Trick2012-02-221-0/+1
| | | | | | | | | | | | Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151135 91177308-0d34-0410-b5e6-96231b3b80d8
* Add API "handleMoveIntoBundl" for updating liveness when moving instructions ↵Lang Hames2012-02-211-1/+9
| | | | | | | | | | | | | | into bundles. This method takes a bundle start and an MI being bundled, and makes the intervals for the MI's operands appear to start/end on the bundle start. Also fixes some minor cosmetic issues (whitespace, naming convention) in the HMEditor code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151099 91177308-0d34-0410-b5e6-96231b3b80d8
* Clear virtual registers after they are no longer referenced.Andrew Trick2012-02-211-0/+3
| | | | | | | | | | | | | Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0. This makes sharing code for pre/postRA passes more robust. Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA(). To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs(). PEI resets virtual regs when it's done scavenging. PTX will either have to provide its own PEI pass or assign physregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151032 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-02-211-26/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151030 91177308-0d34-0410-b5e6-96231b3b80d8
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