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* [AArch64] Add support for NEON scalar negate instruction.Chad Rosier2013-10-161-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar absolute value instruction.Chad Rosier2013-10-161-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comment.Chad Rosier2013-10-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed saturating accumulated of unsignedChad Rosier2013-10-161-0/+5
| | | | | | value and unsigned saturating accumulate of signed value instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
* TypeFinder: prefer iterative algorithm to keep stack usage low.Will Dietz2013-10-161-0/+8
| | | | | | | Introduce subtype_reverse_iterator to maintain the numbering assigned during the recursive type walk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192770 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from ↵Craig Topper2013-10-151-3/+0
| | | | | | x86_sse42_crc32_32_8 and was not mapped to a clang builtin. I'm not even sure why this form of the instruction is even called out explicitly in the docs. Also add AutoUpgrade support to convert it into the other intrinsic with appropriate trunc and zext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192672 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-141-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a GlobalAlias::isValidLinkage to reduce code duplication.Rafael Espindola2013-10-091-0/+5
| | | | | | Thanks to Reid Kleckner for the suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192298 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-091-15/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-081-0/+3
| | | | | | reciprocal exponent, and reciprocal square root estimate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix duplicated assertions.Matt Arsenault2013-10-081-27/+21
| | | | | | Do what some other instructions do, and add an assert method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192236 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-081-0/+12
| | | | | | convert instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Downgrade InsertPointGuard's instruction pointer to a raw pointer.Benjamin Kramer2013-10-081-2/+2
| | | | | | | | Sadly this loses the checking from AssertingVH, but apparently storing the end() of a BasicBlock into an AssertingVH has bad consequences as it's not really an instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192209 91177308-0d34-0410-b5e6-96231b3b80d8
* Change objectsize intrinsic to accept different address spaces.Matt Arsenault2013-10-071-1/+1
| | | | | | | Bitcasting everything to i8* won't work. Autoupgrade the old intrinsic declarations to use the new mangling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192117 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-061-0/+30
| | | | | | | Fixed load folding in VPERM2I instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-051-59/+3
| | | | | | are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-051-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for selecting TBM instructions from logical operations. Patch ↵Craig Topper2013-10-031-1/+1
| | | | | | from Yunzhong Gao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
* Add v4f16 to supported value types.Pete Cooper2013-10-031-0/+2
| | | | | | | This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191870 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-011-0/+4
| | | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Add RAII objects to reset insertion points or fast math flags.Benjamin Kramer2013-09-301-0/+48
| | | | | | | | Inspired by the object from the SLPVectorizer. This found a minor bug in the debug loc restoration in the vectorizer where the location of a following instruction was attached instead of the location from the original instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191673 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Move fast math flags to IRBuilderBase.Benjamin Kramer2013-09-301-34/+28
| | | | | | They don't depend on the templated stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191672 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+66
| | | | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-271-0/+3
| | | | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-271-0/+2
| | | | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-271-0/+4
| | | | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-241-8/+4
| | | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-242-6/+76
| | | | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly request unsigned enum types when desiredReid Kleckner2013-09-232-2/+3
| | | | | | | | | | | | | | | | | | | | | The underlying type of all plain enums in MSVC is 'int', even if the enumerator contains large 32-bit unsigned values or values greater than UINT_MAX. The only way to get a large or unsigned enum type is to request it explicitly with the C++11 strong enum types feature. However, since LLVM isn't C++11 yet, I had to add a conditional LLVM_ENUM_INT_TYPE to Compiler.h to control its usage. The motivating true positive for this change is compiling PointerIntPair with MSVC for win64. The PointerIntMask value is supposed to be pointer sized value of all ones with some low zeros. Instead, it's truncated to 32-bits! We are only saved later because it is sign extended back in the AND with int64_t, and we happen to want all ones. This silences lots of -Wmicrosoft warnings during a clang self-host targeting Windows. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191241 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-231-6/+6
| | | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-191-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-181-0/+16
| | | | | | | Patch by Bradley Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
* Add llvm.x86.* intrinsics for Intel SHA ExtensionsBen Langmuir2013-09-171-0/+21
| | | | | | | | | Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as well as tests. Also remove mayLoad and hasSideEffects, which can be inferred from the instruction patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190864 91177308-0d34-0410-b5e6-96231b3b80d8
* Make a more clear AVX-512 section header that matches similar in the file.Craig Topper2013-09-171-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190843 91177308-0d34-0410-b5e6-96231b3b80d8
* MemCpyOptimizer: Use max legal int size instead of pointer sizeMatt Arsenault2013-09-161-0/+11
| | | | | | | | | | | | If there are no legal integers, assume 1 byte. This makes more sense than using the pointer size as a guess for the maximum GPR width. It is conceivable to want to use some 64-bit pointers on a target where 64-bit integers aren't legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190817 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement function prefix data as an IR feature.Peter Collingbourne2013-09-161-3/+10
| | | | | | | | | Previous discussion: http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/063909.html Differential Revision: http://llvm-reviews.chandlerc.com/D1191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190773 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment to match what the assert actually enforcesMatt Arsenault2013-09-121-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190566 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsicsDaniel Sanders2013-09-111-6/+6
| | | | | | | | | The elements of the operands should be half the width of the elements of the result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)Daniel Sanders2013-09-101-4/+0
| | | | | | | | The dotp_[su].b instructions never existed in any revision of the MSA spec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190398 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert patches to add case-range support for PR1255.Bob Wilson2013-09-091-237/+121
| | | | | | | | | | | | | | | | | The work on this project was left in an unfinished and inconsistent state. Hopefully someone will eventually get a chance to implement this feature, but in the meantime, it is better to put things back the way the were. I have left support in the bitcode reader to handle the case-range bitcode format, so that we do not lose bitcode compatibility with the llvm 3.3 release. This reverts the following commits: 155464, 156374, 156377, 156613, 156704, 156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575, 157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884, 157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100, 159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659, 159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190328 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: add isTBAAVtableAccess to MDNode so clients can call the functionManman Ren2013-09-061-0/+3
| | | | | | | | | | | | | | instead of having its own implementation. The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp since it is related to the format of TBAA metadata. The path for struct-path tbaa will be exercised by test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and vptr_update.ll when struct-path tbaa is on by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190216 91177308-0d34-0410-b5e6-96231b3b80d8
* Use type helper functions.Matt Arsenault2013-09-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190113 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-0/+5
| | | | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Add r159136 back now that pr13124 has been fixed."Rafael Espindola2013-09-041-6/+0
| | | | | | | | | | | | | | | | | | | This reverts commit r189886. I found a corner case where this optimization is not valid: Say we have a "linkonce_odr unnamed_addr" in two translation units: * In TU 1 this optimization kicks in and makes it hidden. * In TU 2 it gets const merged with a constant that is *not* unnamed_addr, resulting in a non unnamed_addr constant with default visibility. * The static linker rules for combining visibility them produce a hidden symbol, which is incorrect from the point of view of the non unnamed_addr constant. The one place we can do this is when we know that the symbol is not used from another TU in the same shared object, i.e., during LTO. I will move it there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189954 91177308-0d34-0410-b5e6-96231b3b80d8
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-041-0/+28
| | | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
* Add r159136 back now that pr13124 has been fixed.Rafael Espindola2013-09-031-0/+6
| | | | | | | | | | Original message: If a constant or a function has linkonce_odr linkage and unnamed_addr, mark hidden. Being linkonce_odr guarantees that it is available in every dso that needs it. Being a constant/function with unnamed_addr guarantees that the copies don't have to be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189886 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added IntrNoMem and removed Commutative from sub intrinsics.Daniel Sanders2013-09-031-28/+28
| | | | | | | | | | | | | | | | | | | This changes the SelectionDAG nodes from ISD::INTRINSIC_W_CHAIN to ISD::INTRINSIC_WO_CHAIN which enables easy lowering to equivalent SelectionDAG nodes (e.g. __builtin_msa_sub_w -> ISD::SUB) in future patches since nodes such as ISD::SUB do not have a chain. It also corrects an obvious mistake, namely that the subtract intrinsics were marked as being commutative. As per a similar change in r189106 (http://llvm.org/viewvc/llvm-project?rev=189106&view=rev) there isn’t a new testcase in this patch since the existing tests should test the intrinsics to the same standard and the best I can do for a testcase would be a fragile pass/maybe test of whether memory operations can (and do) cross the intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189784 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added IntrNoMem to the floating-point intrinsics.Daniel Sanders2013-09-031-96/+100
| | | | | | | | | | | | | | | | | This changes the SelectionDAG nodes from ISD::INTRINSIC_W_CHAIN to ISD::INTRINSIC_WO_CHAIN which enables easy lowering to equivalent SelectionDAG nodes (e.g. __builtin_msa_fadd_w -> ISD::FADD) in future patches since nodes such as ISD::FADD do not have a chain. As per a similar change in r189106 (http://llvm.org/viewvc/llvm-project?rev=189106&view=rev) there isn’t a new testcase in this patch since the existing tests should test the intrinsics to the same standard and the best I can do for a testcase would be a fragile pass/maybe test of whether memory operations can (and do) cross the intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189782 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.Tim Northover2013-08-281-6/+0
| | | | | | | Clang is now generating cleaner IR, so this removes the old variants which should be completely unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189481 91177308-0d34-0410-b5e6-96231b3b80d8
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