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path: root/include/llvm/Target/TargetInstrInfo.h
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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-18/+16
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-4/+13
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-9/+203
* Bring in fixes for Cortex-A53 errata + build updates.Stephen Hines2014-10-171-0/+9
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-1/+17
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-9/+9
* Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-171-0/+17
* Fix the ExecutionDepsFix pass to handle AVX instructions.Andrew Trick2013-10-141-0/+20
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+2
* mi-sched: Load clustering is a bit to expensive to enable unconditionally.Andrew Trick2013-09-041-0/+2
* [SystemZ] Remove no-op MVCsRichard Sandiford2013-07-051-0/+8
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-161-16/+0
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-5/+3
* Add a comment to TargetInstrInfo about FoldImmediateHal Finkel2013-04-061-0/+4
* Clean up some confusing language, and use more realistic examples.Jakob Stoklund Olesen2013-04-051-5/+4
* Sort the #include lines for the include/... tree with the script.Chandler Carruth2012-12-031-1/+1
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-3/+0
* Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class.Jakob Stoklund Olesen2012-11-281-102/+27
* Work around a layering violation from Target to CodeGen.Benjamin Kramer2012-11-161-1/+1
* misched: rename interfaceto avoid gcc warningsAndrew Trick2012-11-121-3/+3
* misched: Target-independent support for MacroFusion.Andrew Trick2012-11-121-0/+7
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-0/+13
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-9/+0
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-181-0/+3
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-3/+0
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-171-0/+3
* Mark unimplemented copy constructors and copy assignment operators as LLVM_DE...Craig Topper2012-09-171-2/+2
* Add a bit of documentation to copyPhysReg.Jakob Stoklund Olesen2012-08-291-0/+7
* Simplify the computeOperandLatency API.Andrew Trick2012-08-231-14/+0
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-161-0/+45
* Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen2012-08-131-8/+0
* Minor cleanup of defaultDefLatency APIAndrew Trick2012-08-081-1/+2
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-021-1/+5
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-021-0/+11
* Revert r160920 and r160919 due to dragonegg and clang selfhost failureManman Ren2012-07-291-11/+0
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-07-281-0/+11
* Add an experimental early if-conversion pass, off by default.Jakob Stoklund Olesen2012-07-041-0/+50
* Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-07-021-1/+3
* Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren2012-06-291-8/+11
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-291-3/+1
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-291-1/+3
* *typo: Cyles changed to CyclesKay Tiong Khoo2012-06-131-2/+2
* Removing strange "using" declarations form TargetInstrInfo.Andrew Trick2012-06-081-4/+0
* TargetInstrInfo hooks implemented in codegen should be declared pure virtual.Andrew Trick2012-06-081-6/+26
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-071-0/+9
* Revert r157755.Manman Ren2012-06-061-8/+0
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-9/+31
* X86: replace SUB with CMP if possibleManman Ren2012-05-311-0/+8
* misched: Added ScoreboardHazardRecognizer.Andrew Trick2012-05-241-0/+11
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+2