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path: root/include/llvm/Target/TargetSelectionDAG.td
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* Add ISD::FROUND for libm round()Hal Finkel2013-08-071-0/+1
| | | | | | | | | | | | | | | All libm floating-point rounding functions, except for round(), had their own ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm adding ISD::FROUND so that round() can be custom lowered as well. For the most part, this is straightforward. I've added an intrinsic and a matching ISD node just like those for nearbyint() and friends. The SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed fround). This will be used by the PowerPC backend in a follow-up commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
* Create an FPOW SDNode opcode def in the target independent .td file rather ↵Owen Anderson2013-05-221-0/+1
| | | | | | than in a specific backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182450 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-201-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-281-2/+2
| | | | | | | | | | | | | | | These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-041-0/+3
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach2012-07-171-0/+7
| | | | | | | | | | | | | | | | | | | Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman2012-05-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-111-0/+2
| | | | | | | but it generates int3 on x86 instead of ud2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve generated code for extending loads and some trunc stores on ARM.James Molloy2012-02-201-0/+45
| | | | | | | Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
* CR fixes per Bruno's request.Nadav Rotem2011-09-111-1/+5
| | | | | | | | | Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
* Basic x86 code generation for atomic load and store instructions.Eli Friedman2011-08-241-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an fma TableGen node.Cameron Zwarich2011-07-081-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134762 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-2/+2
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
* FGETSIGN support for x86, using movmskps/pd. Will be enabled with aStuart Hastings2011-06-011-0/+1
| | | | | | | patch to TargetLowering.cpp. rdar://problem/5660695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
* Let the immediate leaf pattern take transforms and switch the signedEric Christopher2011-04-281-2/+2
| | | | | | | | | immediate patterns in arm to using the pattern. Handles rdar://9299434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new bit that ImmLeaf's can opt into, which allows them to duck out ofChris Lattner2011-04-181-1/+7
| | | | | | | | | the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
* since the VT is fixed for a ImmLeaf, there is no reason to expose it to the ↵Chris Lattner2011-04-171-2/+1
| | | | | | matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677 91177308-0d34-0410-b5e6-96231b3b80d8
* now that predicates have a decent abstraction layer on them, introduce a new Chris Lattner2011-04-171-0/+17
| | | | | | | | | | kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework our internal representation of node predicates to expose moreChris Lattner2011-04-171-1/+13
| | | | | | | | | structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-261-0/+1
| | | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene2011-01-261-4/+10
| | | | | | | | | implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Fix a typo in the extract subvector type constraints to specifyDavid Greene2011-01-251-2/+2
| | | | | | | the correct number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124234 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Add TableGen classes for vector/subvector type constraints.David Greene2011-01-251-0/+14
| | | | | | | | | This will be used to check patterns referencing a forthcoming INSERT_SUBVECTOR SDNode and will also be used to check EXTRACT_SUBVECTOR nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124191 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson2011-01-071-0/+3
| | | | | | | | | | | | | | | Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefetch has a MemOperand now. FileCheckize a test.Dale Johannesen2010-11-191-1/+2
| | | | | | | | This finishes up 8460971. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119848 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-031-18/+18
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
* Grammar.Jim Grosbach2010-10-151-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116557 91177308-0d34-0410-b5e6-96231b3b80d8
* add a common SDPatternOperator base class to SDNode and PatFrag forChris Lattner2010-10-071-2/+7
| | | | | | | | stuff that wants to take one or the other. These can both be used as the operation of a dag in a pattern match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115877 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-0/+2
| | | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
* finally remove the immAllOnesV_bc/immAllZerosV_bc patternsChris Lattner2010-03-281-7/+0
| | | | | | | | | | | | and those derived from them. These are obnoxious because they were written as: PatLeaf<(bitconvert). Not having an argument was foiling adding better type checking for operand count matching up with what was required (in this case, bitconvert always requires an operand!) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99759 91177308-0d34-0410-b5e6-96231b3b80d8
* add some node definitions.Chris Lattner2010-03-281-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99745 91177308-0d34-0410-b5e6-96231b3b80d8
* remove parallel support.Chris Lattner2010-03-271-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99703 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-0/+1
| | | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
* Make default expansion for FP16 <-> FP32 nodes into libcallsAnton Korobeynikov2010-03-141-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98501 91177308-0d34-0410-b5e6-96231b3b80d8
* remove a dead PatLeaf, I previously changed all uses to use -1 instead.Chris Lattner2010-02-251-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97148 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate some uses of immAllOnes, just use -1, it doesChris Lattner2010-02-211-1/+1
| | | | | | | | the same thing and is more efficient for the matcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96713 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the CPAttrParentAsRoot code, which is unused, and inconvenientDan Gohman2010-01-041-8/+1
| | | | | | | for a refactoring I'm working on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92503 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman2009-11-231-7/+0
| | | | | | | | | Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a couple more target nodesNate Begeman2009-11-031-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85857 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85556 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.Bob Wilson2009-08-121-2/+5
| | | | | | | | | There have been a few times where I've wanted this but ended up leaving the operand type unconstrained. It is easy to add this now and should help catch errors in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78849 91177308-0d34-0410-b5e6-96231b3b80d8
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-37/+37
| | | | | | | | | while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-37/+37
| | | | | | own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
* Major calling convention code refactoring.Dan Gohman2009-08-051-1/+0
| | | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
* Make IntInits and ListInits typed. This helps deduce types of !if andDavid Greene2009-06-081-0/+1
| | | | | | | | | other operators. For the rare cases where a list type cannot be deduced, provide a []<type> syntax, where <type> is the list element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-6/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
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