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* Added getDefaultSubtargetFeatures method to SubtargetFeatures class which ret...Viktor Kutuzov2009-11-181-0/+5
* Add a target hook to allow changing the tail duplication limit based on theBob Wilson2009-11-181-0/+7
* The llvm-gcc front-end and the pass manager use two separate TargetData objects.Bill Wendling2009-11-181-2/+3
* Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to repl...Evan Cheng2009-11-141-0/+5
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-2/+5
* Allow target to specify regclass for which antideps will only be broken along...David Goodwin2009-11-131-3/+5
* Fix a bootstrap failure.David Greene2009-11-131-0/+16
* Make the MachineFunction argument of getFrameRegister const.David Greene2009-11-121-1/+2
* Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether aDavid Greene2009-11-121-0/+22
* Mark DBG_LABEL, EH_LABEL, and GC_LABEL as not-duplicable, sinceDan Gohman2009-11-121-0/+3
* isLegalICmpImmediate should take a signed integer; code clean up.Evan Cheng2009-11-121-1/+1
* Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be ...Evan Cheng2009-11-111-0/+8
* Fixed to address code review. No functional changes.David Goodwin2009-11-101-9/+4
* Allow targets to specify register classes whose member registers should not b...David Goodwin2009-11-101-2/+7
* fix some bogus asserts, PR5049Chris Lattner2009-11-091-4/+4
* all targets should be required to declare legal integer types. My plan toChris Lattner2009-11-071-11/+10
* add the ability for TargetData to return information about legal integerChris Lattner2009-11-071-8/+27
* more cleanup.Chris Lattner2009-11-071-22/+14
* rewrite TargetData to use StringRef/raw_ostream instead of thrashing std::str...Chris Lattner2009-11-071-2/+2
* Missed this.Evan Cheng2009-11-071-1/+12
* Add code to check at SelectionDAGISel::LowerArguments time to see if return v...Kenneth Uildriks2009-11-071-0/+12
* Pass StringRef by value.Daniel Dunbar2009-11-062-8/+8
* Reintroduce support for overloading target intrinsicsMon P Wang2009-11-051-1/+18
* Add a couple more target nodesNate Begeman2009-11-031-0/+2
* Fix MachineLICM to use the correct virtual register class whenDan Gohman2009-10-301-2/+5
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+4
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-293-8/+9
* Add a second ValueType argument to isFPImmLegal.Evan Cheng2009-10-281-1/+1
* Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which return...Evan Cheng2009-10-271-14/+5
* - Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests andEvan Cheng2009-10-261-19/+9
* Move DataTypes.h to include/llvm/System, update all users. This breaks the lastChandler Carruth2009-10-263-3/+3
* Add isIdentityCopy to check for identity copy (or extract_subreg, etc.)Evan Cheng2009-10-251-9/+19
* Identity copies should not contribute to spill weight.Evan Cheng2009-10-231-2/+23
* Allow the target to select the level of anti-dependence breaking that should ...David Goodwin2009-10-221-2/+8
* Wire up the ARM MCInst printer, for llvm-mc.Daniel Dunbar2009-10-201-1/+10
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-11/+4
* Change createPostRAScheduler so it can be turned off at llc -O1.Evan Cheng2009-10-161-3/+8
* Add a CodeGenOpt::Less level to match -O1. It'll be used by clients which do ...Evan Cheng2009-10-161-3/+4
* Clean up TargetIntrinsicInfo API. Add pure virtual methods.Jakob Stoklund Olesen2009-10-151-24/+10
* Revert the kludge in 76703. I got a cleanDale Johannesen2009-10-121-6/+0
* Replace X86's CanRematLoadWithDispOperand by calling the target-independentDan Gohman2009-10-101-2/+3
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-11/+21
* Add a const qualifier.Dan Gohman2009-10-091-1/+1
* Re-enable register scavenging in Thumb1 by default.Jim Grosbach2009-10-081-0/+6
* reverting thumb1 scavenging default due to test failure while I figure out wh...Jim Grosbach2009-10-071-6/+0
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-071-0/+6
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-071-10/+0
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-2/+7
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-0/+18
* remove trailing whitespaceJim Grosbach2009-10-011-19/+19