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* Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen2012-08-131-8/+0
| | | | | | | | | | | | | | | It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow legalization of target-specific SDNodes, provided that the target ↵Owen Anderson2012-08-081-1/+3
| | | | | | itself provide a legalization hook for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161536 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-081-0/+1
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanup of defaultDefLatency APIAndrew Trick2012-08-081-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161470 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r161371. Removing the 'const' before Type is a "good thing".Bill Wendling2012-08-071-13/+13
| | | | | | | | | | --- Reverse-merging r161371 into '.': U include/llvm/Target/TargetData.h U lib/Target/TargetData.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161394 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify the Type parameter to some methods (which are const anyway).Bill Wendling2012-08-071-13/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161371 91177308-0d34-0410-b5e6-96231b3b80d8
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-041-0/+3
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to reduce the compile time impact of r161232.Bob Wilson2012-08-031-0/+25
| | | | | | | | | | | | The previous change caused fast isel to not attempt handling any calls to builtin functions. That included things like "printf" and caused some noticable regressions in compile time. I wanted to avoid having fast isel keep a separate list of functions that had to be kept in sync with what the code in SelectionDAGBuilder.cpp was handling. I've resolved that here by moving the list into TargetLibraryInfo. This is somewhat redundant in SelectionDAGBuilder but it will ensure that we keep things consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161263 91177308-0d34-0410-b5e6-96231b3b80d8
* Fall back to selection DAG isel for calls to builtin functions.Bob Wilson2012-08-031-1/+3
| | | | | | | | | | Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new getLibFunc method to TargetLibraryInfo.Bob Wilson2012-08-031-67/+71
| | | | | | | | This just provides a way to look up a LibFunc::Func enum value for a function name. Alphabetize the enums and function names so we can use a binary search. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161231 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-021-1/+5
| | | | | | | | | | | Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetRegisterInfo::hasRegUnit().Jakob Stoklund Olesen2012-08-021-0/+8
| | | | | | | This trivial helper function tests if a register contains a register unit. It is similar to regsOverlap(), but with asymmetric arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161180 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-021-0/+11
| | | | | | | | | | | | | Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Eric Christopher2012-07-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160981 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r160920 and r160919 due to dragonegg and clang selfhost failureManman Ren2012-07-291-11/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-07-281-0/+11
| | | | | | | | | | Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove support for 'CompositeIndices' and sub-register cycles.Jakob Stoklund Olesen2012-07-261-15/+0
| | | | | | | | | | | | Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone, there is no longer a need for the CompositeIndices construct in .td files. Sub-register index composition can be specified on the SubRegIndex itself using the ComposedOf field. Also enforce unique names for sub-registers in TableGen. The same sub-register cannot be available with multiple sub-register indexes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160842 91177308-0d34-0410-b5e6-96231b3b80d8
* make all Emit*() functions consult the TargetLibraryInfo information before ↵Nuno Lopes2012-07-251-0/+2
| | | | | | | | | creating a call to a library function. Update all clients to pass the TLI information around. Previous draft reviewed by Eli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160733 91177308-0d34-0410-b5e6-96231b3b80d8
* add a few more functions to TargetLibraryInfo:Nuno Lopes2012-07-241-0/+14
| | | | | | fputc, memchr, memcmp, putchar, puts, strchr, strncmp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160690 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetLibraryInfo: add strn?cat, strn?cpy, and strn?lenNuno Lopes2012-07-241-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160678 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
* Make RegisterOperand a subclass of DAGOperand so that RegisterOperands can ↵Owen Anderson2012-07-201-1/+2
| | | | | | be passed into multiclasses that take DAGOperands as multiclass parameters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160540 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tabs.Bill Wendling2012-07-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160473 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach2012-07-171-0/+7
| | | | | | | | | | | | | | | | | | | Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-073-127/+163
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-07-071-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an experimental early if-conversion pass, off by default.Jakob Stoklund Olesen2012-07-041-0/+50
| | | | | | | | | | | | | This pass performs if-conversion on SSA form machine code by speculatively executing both sides of the branch and using a cmov instruction to select the result. This can help lower the number of branch mispredictions on architectures like x86 that don't have predicable instructions. The current implementation is very aggressive, and causes regressions on mosts tests. It needs good heuristics that have yet to be implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159694 91177308-0d34-0410-b5e6-96231b3b80d8
* Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng2012-07-022-6/+17
| | | | | | instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend TargetPassConfig to allow running only a subset of the normal passes.Bob Wilson2012-07-021-2/+7
| | | | | | | | | | | | | | | | | This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-07-022-10/+13
| | | | | | Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren2012-06-291-8/+11
| | | | | | | instructions with two register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-292-13/+10
| | | | | | This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-292-10/+13
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
* Define DAGOperand, an empty base class for RegisterClass and Operand. This ↵Owen Anderson2012-06-251-2/+9
| | | | | | allows one to write multiclasses that are polymorphic over both registers and non-register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159162 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: AsmMatcher support for better operand diagnostics.Jim Grosbach2012-06-221-0/+5
| | | | | | | | | | | | | "Invalid operand" may be a completely correct diagnostic, but it's often insufficiently specific to really help identify and fix the problem in assembly source. Allow a target to specify a more-specific diagnostic kind for each AsmOperandClass derived definition and use that to provide more detailed diagnostics when an operant of that class resulted in a match failure. rdar://8987109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159050 91177308-0d34-0410-b5e6-96231b3b80d8
* Use "NoItineraries" for processors with no itineraries.Andrew Trick2012-06-221-1/+2
| | | | | | | | This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames2012-06-221-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DAG-combines for aggressive FMA formation.Lang Hames2012-06-191-8/+8
| | | | | | | | | | | | | | | | | | | | | | This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the support for using .init_array from ARM to the genericRafael Espindola2012-06-191-1/+5
| | | | | | | | | | TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
* *typo: Cyles changed to CyclesKay Tiong Khoo2012-06-131-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158404 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert comments to proper Doxygen comments.Dmitri Gribenko2012-06-092-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158248 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing strange "using" declarations form TargetInstrInfo.Andrew Trick2012-06-081-4/+0
| | | | | | I can't imagine why these were added. Trial and error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158247 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetInstrInfo hooks implemented in codegen should be declared pure virtual.Andrew Trick2012-06-081-6/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158233 91177308-0d34-0410-b5e6-96231b3b80d8
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-071-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r157755.Manman Ren2012-06-061-8/+0
| | | | | | | | | The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-9/+31
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new intrinsic: llvm.fmuladd. This intrinsic represents a multiply-addLang Hames2012-06-051-0/+8
| | | | | | | | | | | | | | expression (a * b + c) that can be implemented as a fused multiply-add (fma) if the target determines that this will be more efficient. This intrinsic will be used to implement FP_CONTRACT support and an aggressive FMA formation mode. If your target has a fast FMA instruction you should override the isFMAFasterThanMulAndAdd method in TargetLowering to return true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158014 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-051-1/+20
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-06-051-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the "-promote-elements" flag. This flag is now enabled by default.Nadav Rotem2012-06-041-10/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157925 91177308-0d34-0410-b5e6-96231b3b80d8
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