| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner... | Daniel Dunbar | 2010-06-23 | 1 | -2/+4 |
| * | Some targets don't require the fencing MEMBARRIER instructions surrounding | Jim Grosbach | 2010-06-23 | 1 | -0/+18 |
| * | remove trailing whitespace | Jim Grosbach | 2010-06-23 | 1 | -85/+85 |
| * | Tail merging pass shall not break up IT blocks. rdar://8115404 | Evan Cheng | 2010-06-22 | 1 | -0/+8 |
| * | Remove isTwoAddress from llvm. | Eric Christopher | 2010-06-21 | 1 | -1/+0 |
| * | Allow ARM if-converter to be run after post allocation scheduling. | Evan Cheng | 2010-06-18 | 1 | -0/+18 |
| * | Start TargetRegisterClass indices at 0 instead of 1, so that | Dan Gohman | 2010-06-18 | 2 | -3/+3 |
| * | Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, | Dan Gohman | 2010-06-18 | 1 | -4/+2 |
| * | Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This | Stuart Hastings | 2010-06-17 | 1 | -2/+3 |
| * | Fix a comment typo. | Bob Wilson | 2010-06-14 | 1 | -1/+1 |
| * | declare a class with 'class' instead of struct to avoid tag mismatch | Chris Lattner | 2010-06-12 | 1 | -1/+2 |
| * | Allow target to provide its own hazard recognizer to post-ra scheduler. | Evan Cheng | 2010-06-12 | 1 | -0/+11 |
| * | Allow target to place 2-address pass inserted copies in better spots. Thumb2 ... | Evan Cheng | 2010-06-09 | 1 | -0/+8 |
| * | - Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it | Bill Wendling | 2010-06-09 | 1 | -10/+9 |
| * | Reapply r105521, this time appending "LLU" to 64 bit | Bruno Cardoso Lopes | 2010-06-08 | 2 | -2/+4 |
| * | revert r105521, which is breaking the buildbots with stuff like this: | Chris Lattner | 2010-06-05 | 2 | -4/+2 |
| * | Initial AVX support for some instructions. No patterns matched | Bruno Cardoso Lopes | 2010-06-05 | 2 | -2/+4 |
| * | Slightly change the meaning of the reMaterialize target hook when the original | Jakob Stoklund Olesen | 2010-06-02 | 1 | -2/+5 |
| * | Rename canCombinedSubRegIndex method to something more grammatically correct | Bob Wilson | 2010-06-02 | 1 | -8/+9 |
| * | Remove uses of getCalleeSavedRegClasses from outside the | Rafael Espindola | 2010-06-02 | 1 | -5/+4 |
| * | Add a TargetRegisterInfo::composeSubRegIndices hook with a default | Jakob Stoklund Olesen | 2010-05-28 | 1 | -0/+17 |
| * | MC: Add TargetMachine support for setting the value of MCRelaxAll with | Daniel Dunbar | 2010-05-26 | 1 | -1/+11 |
| * | MC: Change RelaxInstruction to only take the input and output instructions. | Daniel Dunbar | 2010-05-26 | 1 | -4/+6 |
| * | MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it | Daniel Dunbar | 2010-05-26 | 1 | -4/+1 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -11/+17 |
| * | MC: Eliminate MCAsmFixup, replace with MCFixup. | Daniel Dunbar | 2010-05-26 | 1 | -3/+3 |
| * | Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." | Jakob Stoklund Olesen | 2010-05-26 | 1 | -17/+11 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -11/+17 |
| * | Drop the SuperregHashTable. It is essentially the same as SubregHashTable. | Jakob Stoklund Olesen | 2010-05-25 | 1 | -17/+1 |
| * | Print symbolic SubRegIndex names on machine operands. | Jakob Stoklund Olesen | 2010-05-25 | 1 | -0/+9 |
| * | Remove NumberHack entirely. | Jakob Stoklund Olesen | 2010-05-25 | 1 | -5/+1 |
| * | Switch SubRegSet to using symbolic SubRegIndices | Jakob Stoklund Olesen | 2010-05-24 | 1 | -2/+3 |
| * | Replace the tablegen RegisterClass field SubRegClassList with an alist-like data | Jakob Stoklund Olesen | 2010-05-24 | 2 | -6/+3 |
| * | Add the SubRegIndex TableGen class. | Jakob Stoklund Olesen | 2010-05-24 | 1 | -0/+8 |
| * | tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses ins... | Daniel Dunbar | 2010-05-22 | 1 | -6/+6 |
| * | Implement @llvm.returnaddress. rdar://8015977. | Evan Cheng | 2010-05-22 | 1 | -2/+4 |
| * | Add a new section and accessor for TLS data. | Eric Christopher | 2010-05-22 | 1 | -0/+7 |
| * | Currently, createMachOStreamer() is invoked directly in llvm-mc which | Matt Fleming | 2010-05-21 | 1 | -0/+46 |
| * | Allow targets more controls on what nodes are scheduled by reg pressure, what... | Evan Cheng | 2010-05-20 | 2 | -0/+8 |
| * | tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor | Daniel Dunbar | 2010-05-20 | 1 | -0/+3 |
| * | Add a hybrid bottom up scheduler that reduce register usage while avoiding | Evan Cheng | 2010-05-20 | 1 | -1/+2 |
| * | Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMa... | Evan Cheng | 2010-05-19 | 2 | -8/+10 |
| * | Allow TargetLowering::getRegClassFor() to be called on illegal types. Also | Evan Cheng | 2010-05-15 | 1 | -2/+2 |
| * | Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE | Evan Cheng | 2010-05-14 | 1 | -0/+12 |
| * | Get rid of the bit twiddling to read / set OpActions and ValueTypeActions. Th... | Evan Cheng | 2010-05-14 | 1 | -26/+10 |
| * | Eliminate use of magic numbers to access OpActions. It also has the effect of... | Evan Cheng | 2010-05-13 | 1 | -5/+7 |
| * | Fix up LoadExtActions, TruncStoreActions, and IndexedModeActions representati... | Evan Cheng | 2010-05-13 | 1 | -47/+47 |
| * | 80 col violation. | Evan Cheng | 2010-05-13 | 1 | -1/+2 |
| * | MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can | Daniel Dunbar | 2010-05-12 | 1 | -0/+8 |
| * | Remove the "WantsWholeFile" concept, as it's no longer needed. CBE | Dan Gohman | 2010-05-11 | 1 | -11/+0 |
