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path: root/lib/CodeGen/MachineRegisterInfo.cpp
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* Remove RegClass2VRegMap from MachineRegisterInfo.Evan Cheng2011-06-271-14/+0
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+2
* Revert r124611 - "Keep track of incoming argument's location while emitting L...Devang Patel2011-02-211-8/+1
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-311-1/+8
* Use IndexedMap for MachineRegisterInfo as well. No functional change.Jakob Stoklund Olesen2011-01-091-19/+22
* Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen2010-10-061-0/+14
* Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen2010-07-101-6/+3
* Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman2010-06-241-14/+25
* Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman2010-06-181-0/+1
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-2/+2
* Remove unused function.Benjamin Kramer2010-05-291-69/+0
* Remove schedule-livein-copies. It's not being used.Evan Cheng2010-05-291-30/+12
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-241-0/+9
* Add a utility function for conservatively clearing kill flags, and makeDan Gohman2010-05-131-0/+9
* Silence warningJakob Stoklund Olesen2010-05-111-1/+1
* Simplify the tracking of used physregs to a bulk bitor followed by a transitiveJakob Stoklund Olesen2010-05-111-0/+9
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+4
* Replace r102368 with code that's less fragile. This creates DBG_VALUE instruc...Evan Cheng2010-04-281-28/+9
* Insert dbg_value instructions for function entry block liveins (i.e. function...Evan Cheng2010-04-261-1/+30
* Move the code for initialing the entry block livein set out ofDan Gohman2010-04-141-0/+5
* Move the code for emitting livein copies out of SelectionDAGISel.Dan Gohman2010-04-141-0/+106
* Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.Dan Gohman2010-04-131-0/+14
* Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng2010-03-031-0/+13
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-251-5/+3
* Part 1.Evan Cheng2009-06-151-1/+1
* Move register allocation preference (or hint) from LiveInterval to MachineReg...Evan Cheng2009-06-141-0/+2
* Move MachineRegisterInfo::setRegClass out of line.Dan Gohman2009-04-151-0/+20
* Move createVirtualRegister out-of-line.Dan Gohman2008-12-081-0/+18
* Add a register class -> virtual registers map.Evan Cheng2008-10-201-0/+1
* Assert that all MachineInstrs update PhysRegUseDefLists inDan Gohman2008-07-071-0/+3
* Added debugging routine dumpUses.Evan Cheng2008-02-131-0/+8
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-5/+5
* switch the register iterator to act more like hte LLVM value iterator: derefe...Chris Lattner2008-01-011-2/+16
* Add a trivial but handy function to efficiently return the machine Chris Lattner2008-01-011-0/+15
* Implement automatically updated def/use lists for all MachineInstr register Chris Lattner2008-01-011-1/+27
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-0/+20
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