external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix a typo (the the => the)	Sylvestre Ledru	2012-07-23	1	-1/+1
*	I'm introducing a new machine model to simultaneously allow simple	Andrew Trick	2012-07-07	1	-1/+2
*	misched: allow NULL InstrItineraries.	Andrew Trick	2012-07-02	1	-0/+1
*	misched: avoid scheduling instructions that can't be dispatched.	Andrew Trick	2012-06-29	1	-6/+29
*	misched: count micro-ops toward the issue limit.	Andrew Trick	2012-06-29	1	-10/+19
*	Guard private fields that are unused in Release builds with #ifndef NDEBUG.	Benjamin Kramer	2012-06-16	1	-1/+7
*	Move RegisterClassInfo.h.	Andrew Trick	2012-06-06	1	-1/+1
*	Move RegisterPressure.h.	Andrew Trick	2012-06-06	1	-1/+1
*	misched: API for minimum vs. expected latency.	Andrew Trick	2012-06-05	1	-31/+81
*	misched: comments from code review.	Andrew Trick	2012-06-05	1	-3/+3
*	misched: trace formatting	Andrew Trick	2012-05-25	1	-6/+5
*	Silence unused variable warnings from when assertions are disabled.	Kaelyn Uhrain	2012-05-24	1	-0/+2
*	misched: Use the same scheduling heuristics with -misched-topdown/bottomup.	Andrew Trick	2012-05-24	1	-2/+16
*	misched: Trace regpressure.	Andrew Trick	2012-05-24	1	-2/+4
*	misched: Give each ReadyQ a unique ID	Andrew Trick	2012-05-24	1	-36/+45
*	misched: Added ScoreboardHazardRecognizer.	Andrew Trick	2012-05-24	1	-49/+232
*	misched: Release bottom roots in reverse order.	Andrew Trick	2012-05-24	1	-9/+23
*	misched: rename ReadyQ class	Andrew Trick	2012-05-24	1	-8/+9
*	misched: copy comments so compareRPDelta is readable by itself.	Andrew Trick	2012-05-24	1	-1/+4
*	comments	Andrew Trick	2012-05-17	1	-2/+3
*	misched: trace ReadyQ.	Andrew Trick	2012-05-17	1	-0/+8
*	misched: Added 3-level regpressure back-off.	Andrew Trick	2012-05-17	1	-36/+184
*	comment	Andrew Trick	2012-05-17	1	-2/+0
*	misched: fix liveness iterators	Andrew Trick	2012-05-17	1	-10/+16
*	misched: Print machineinstrs with -debug-only=misched	Andrew Trick	2012-05-10	1	-0/+2
*	misched: tracing register pressure heuristics.	Andrew Trick	2012-05-10	1	-6/+22
*	misched: Add register pressure backoff to ConvergingScheduler.	Andrew Trick	2012-05-10	1	-38/+144
*	misched: Release only unscheduled nodes into ReadyQ.	Andrew Trick	2012-05-10	1	-2/+8
*	misched: Added ReadyQ container wrapper for Top and Bottom Queues.	Andrew Trick	2012-05-10	1	-11/+44
*	misched: Introducing Top and Bottom register pressure trackers during schedul...	Andrew Trick	2012-05-10	1	-10/+71
*	Fix a naughty header include that breaks "installed" builds.	Andrew Trick	2012-04-24	1	-2/+12
*	misched: try (not too hard) to place debug values where they belong	Andrew Trick	2012-04-24	1	-0/+25
*	misched: ignore debug values during scheduling	Andrew Trick	2012-04-24	1	-6/+31
*	misched: DAG builder support for tracking register pressure within the curren...	Andrew Trick	2012-04-24	1	-4/+48
*	misched: Add finalizeScheduler to complete the target interface.	Andrew Trick	2012-04-01	1	-0/+1
*	misched: trace LiveIntervals after scheduling.	Andrew Trick	2012-03-21	1	-0/+1
*	misched: obvious iterator update fixes for bottom-up.	Andrew Trick	2012-03-21	1	-0/+6
*	misched: cleanup main loop	Andrew Trick	2012-03-21	1	-10/+14
*	Add an option to the MI scheduler to cut off scheduling after a fixed number of	Lang Hames	2012-03-19	1	-1/+19
*	Silence operator precedence warnings.	Benjamin Kramer	2012-03-14	1	-3/+3
*	misched: implemented a framework for top-down or bottom-up scheduling.	Andrew Trick	2012-03-14	1	-98/+266
*	misched comments	Andrew Trick	2012-03-14	1	-0/+15
*	misched: handle scheduler that insert instructions at empty region boundaries.	Andrew Trick	2012-03-09	1	-3/+12
*	misched: handle scheduling region boundaries nicely.	Andrew Trick	2012-03-09	1	-4/+11
*	misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...	Andrew Trick	2012-03-09	1	-3/+3
*	misched comments	Andrew Trick	2012-03-09	1	-2/+3
*	revert 152356: verify misched changes using -misched=shuffle.	Andrew Trick	2012-03-09	1	-3/+3
*	misched: allow the default scheduler to be one chosen by the target.	Andrew Trick	2012-03-09	1	-16/+33
*	Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().	Evan Cheng	2012-03-09	1	-3/+3
*	misched interface: Expose the MachineScheduler pass.	Andrew Trick	2012-03-08	1	-144/+102