| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | misched: disable SSA check pending PR13112. | Andrew Trick | 2012-06-14 | 1 | -2/+4 |
| * | sched: fix latency of memory dependence chain edges for consistency. | Andrew Trick | 2012-06-13 | 1 | -13/+21 |
| * | Move RegisterPressure.h. | Andrew Trick | 2012-06-06 | 1 | -1/+1 |
| * | Remove unused private fields found by clang's new -Wunused-private-field. | Benjamin Kramer | 2012-06-06 | 1 | -1/+1 |
| * | misched: API for minimum vs. expected latency. | Andrew Trick | 2012-06-05 | 1 | -61/+18 |
| * | Switch all register list clients to the new MC*Iterator interface. | Jakob Stoklund Olesen | 2012-06-01 | 1 | -2/+4 |
| * | Use LiveRangeQuery in ScheduleDAGInstrs. | Jakob Stoklund Olesen | 2012-05-20 | 1 | -11/+3 |
| * | Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside MachineSche... | Andrew Trick | 2012-05-15 | 1 | -22/+243 |
| * | misched: DAG builder must special case earlyclobber | Andrew Trick | 2012-04-24 | 1 | -0/+9 |
| * | misched: DAG builder support for tracking register pressure within the curren... | Andrew Trick | 2012-04-24 | 1 | -1/+10 |
| * | New and improved comment. | Andrew Trick | 2012-04-20 | 1 | -1/+1 |
| * | SparseSet: Add support for key-derived indexes and arbitrary key types. | Andrew Trick | 2012-04-20 | 1 | -2/+2 |
| * | misched: initialize BB | Andrew Trick | 2012-04-20 | 1 | -2/+4 |
| * | misched: Added CanHandleTerminators. | Andrew Trick | 2012-04-13 | 1 | -3/+3 |
| * | ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th... | Benjamin Kramer | 2012-03-16 | 1 | -2/+2 |
| * | misched: add DAG edges from vreg defs to ExitSU. | Andrew Trick | 2012-03-16 | 1 | -1/+3 |
| * | misched: implemented a framework for top-down or bottom-up scheduling. | Andrew Trick | 2012-03-14 | 1 | -4/+7 |
| * | misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n... | Andrew Trick | 2012-03-09 | 1 | -5/+5 |
| * | misched prep: Expose the ScheduleDAGInstrs interface so targets may | Andrew Trick | 2012-03-07 | 1 | -1/+1 |
| * | misched prep: Comment the ScheduleDAGInstrs interface. | Andrew Trick | 2012-03-07 | 1 | -2/+3 |
| * | misched prep: Cleanup ScheduleDAGInstrs interface. | Andrew Trick | 2012-03-07 | 1 | -2/+2 |
| * | misched prep: rename InsertPos to End. | Andrew Trick | 2012-03-07 | 1 | -5/+5 |
| * | misched preparation: rename core scheduler methods for consistency. | Andrew Trick | 2012-03-07 | 1 | -13/+13 |
| * | misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. | Andrew Trick | 2012-03-07 | 1 | -20/+29 |
| * | misched preparation: modularize schedule emission. | Andrew Trick | 2012-03-07 | 1 | -35/+0 |
| * | Cleanup in preparation for misched: Move DAG visualization logic. | Andrew Trick | 2012-03-07 | 1 | -0/+6 |
| * | Use uint16_t to store register overlaps to reduce static data. | Craig Topper | 2012-03-04 | 1 | -2/+2 |
| * | PostRA sched: speed up physreg tracking by not abusing SparseSet. | Andrew Trick | 2012-02-24 | 1 | -15/+26 |
| * | misched: cleanup reaching def computation | Andrew Trick | 2012-02-23 | 1 | -3/+5 |
| * | PostRASched: Convert physreg def/use tracking to Jakob's SparseSet. | Andrew Trick | 2012-02-23 | 1 | -78/+86 |
| * | Don't compute latencies for regmask operands. | Jakob Stoklund Olesen | 2012-02-22 | 1 | -1/+3 |
| * | misched: Use SparseSet for VRegDegs for constant time clear(). | Andrew Trick | 2012-02-22 | 1 | -13/+19 |
| * | Comment from code review | Andrew Trick | 2012-02-22 | 1 | -0/+1 |
| * | misched: DAG builder should not track dependencies for SSA defs. | Andrew Trick | 2012-02-22 | 1 | -1/+5 |
| * | Initialize SUnits before DAG building. | Andrew Trick | 2012-02-22 | 1 | -61/+83 |
| * | Clear virtual registers after they are no longer referenced. | Andrew Trick | 2012-02-21 | 1 | -0/+2 |
| * | misched: Initial code for building an MI level scheduling DAG | Andrew Trick | 2012-01-14 | 1 | -8/+86 |
| * | Move physreg dependency generation into aptly named addPhysRegDeps. | Andrew Trick | 2012-01-14 | 1 | -155/+175 |
| * | misched: Added ScheduleDAGInstrs::IsPostRA | Andrew Trick | 2012-01-14 | 1 | -3/+5 |
| * | Added a late machine instruction copy propagation pass. This catches | Evan Cheng | 2012-01-07 | 1 | -6/+1 |
| * | Remove an unused variable. | Chandler Carruth | 2012-01-05 | 1 | -1/+0 |
| * | Minor postra scheduler cleanup. It could result in more precise antidependenc... | Andrew Trick | 2012-01-05 | 1 | -25/+19 |
| * | Model ARM predicated write as read-mod-write. e.g. | Evan Cheng | 2011-12-14 | 1 | -2/+2 |
| * | Allow target to specify register output dependency. Still default to one. | Evan Cheng | 2011-12-14 | 1 | -1/+7 |
| * | - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function | Evan Cheng | 2011-12-14 | 1 | -11/+6 |
| * | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng | 2011-12-07 | 1 | -11/+10 |
| * | First chunk of MachineInstr bundle support. | Evan Cheng | 2011-12-06 | 1 | -1/+1 |
| * | make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instr... | Hal Finkel | 2011-12-02 | 1 | -5/+5 |
| * | PostRA scheduler fix. Clear stale loop dependencies. | Andrew Trick | 2011-10-07 | 1 | -0/+1 |
| * | whitespace | Andrew Trick | 2011-10-07 | 1 | -1/+1 |
