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path: root/lib/CodeGen/ScheduleDAGInstrs.cpp
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* Fix dependencies added to model memory aliasing for post-RA scheduling. The d...David Goodwin2009-11-091-96/+97
* Correctly add chain dependencies around calls and unknown-side-effect instruc...David Goodwin2009-11-051-2/+3
* <rdar://problem/7352605>. When building schedule graph use mayAlias informati...David Goodwin2009-11-031-15/+43
* Chain dependencies used to enforce memory order should have latency of 0 (exc...David Goodwin2009-11-021-14/+23
* When checking whether a def of an aliased register is dead, ask theDan Gohman2009-10-261-1/+1
* Spill slots cannot alias.Evan Cheng2009-10-181-5/+8
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-181-3/+12
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-2/+2
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-071-1/+1
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-6/+7
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ...Evan Cheng2009-09-181-1/+2
* Use the schedule itinerary operand use/def cycle information to adjust depend...David Goodwin2009-08-191-3/+60
* Add callback to allow target to adjust latency of schedule dependency edge.David Goodwin2009-08-131-5/+10
* Post RA scheduler changes. Introduce a hazard recognizer that uses the target...David Goodwin2009-08-101-7/+10
* Fix a typo in a comment.Dan Gohman2009-08-071-1/+1
* Eliminate yet another copy of getOpcode.Dan Gohman2009-07-171-17/+6
* Move isLCSSAForm, isLoopInvariant, getCanonicalInductionVariable,Dan Gohman2009-07-131-0/+1
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-3/+16
* Factor out more code for computing register live-range informationforDan Gohman2009-02-101-120/+40
* Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman2009-02-061-1/+1
* Fix a post-RA scheduling dependency bug.Dan Gohman2009-01-301-11/+90
* Instead of adding dependence edges between terminator instructionsDan Gohman2009-01-161-10/+34
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-18/+21
* Clean up the atomic opcodes in SelectionDAG.Dan Gohman2008-12-231-0/+1
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-231-1/+1
* Use isTerminator() instead of isBranch()||isReturn() inDan Gohman2008-12-231-3/+2
* Add initial support for back-scheduling address computations,Dan Gohman2008-12-161-1/+132
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-161-18/+50
* Add a simple target-independent heuristic to allow targets with noDan Gohman2008-12-161-0/+6
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-091-23/+24
* Fix the top-level comments, and fix some 80-column violations.Dan Gohman2008-12-081-7/+9
* Add minimal support for disambiguating memory references. CurrentlyDan Gohman2008-12-041-13/+123
* Pass the isAntiDep argument.Dan Gohman2008-11-241-1/+1
* Correctly set the isCtrl flag for chain dependencies.Dan Gohman2008-11-211-4/+4
* Update comments.Dan Gohman2008-11-211-9/+9
* Set the isAntiDep flag in the MachineInstr scheduler.Dan Gohman2008-11-211-1/+1
* Use ComputeLatency in the MachineInstr scheduler.Dan Gohman2008-11-211-0/+3
* Implement ComputeLatency for MachineInstr ScheduleDAGs. FactorDan Gohman2008-11-211-1/+10
* Treat mid-block labels the same as terminators when building theDan Gohman2008-11-201-1/+1
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-191-0/+135
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