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path: root/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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* Use empty() instead of comparing size() with zero.Dan Gohman2008-01-291-1/+1
* Fix a typo in a comment.Dan Gohman2008-01-291-1/+1
* Fix a typo in a comment.Dan Gohman2008-01-291-1/+0
* Special copy SUnit's do not have SDNode's.Evan Cheng2008-01-091-2/+2
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-6/+6
* simplify some code.Chris Lattner2008-01-071-10/+13
* Rename all the M_* flags to be namespace qualified enums, and switch Chris Lattner2008-01-071-1/+1
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-9/+10
* Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.Owen Anderson2008-01-071-1/+1
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-1/+0
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* More accurate checks for two-address constraints.Evan Cheng2007-12-201-8/+40
* Bring back a burr scheduling heuristic that's still needed.Evan Cheng2007-12-201-5/+34
* FIX for PR1799: When a load is unfolded from an instruction, check if it is a...Evan Cheng2007-12-181-26/+36
* Bug fix. Passive nodes are not in SUnitMap.Evan Cheng2007-11-091-3/+6
* Add pseudo dependency to force two-address instruction to be scheduled afterEvan Cheng2007-11-061-2/+5
* One mundane change: Change ReplaceAllUsesOfValueWith to *optionally* Chris Lattner2007-10-151-4/+2
* EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG likeEvan Cheng2007-10-121-0/+13
* Fix a typo in a comment.Dan Gohman2007-10-051-1/+1
* Chain producing nodes cannot be moved, not chain reading nodes.Evan Cheng2007-10-051-5/+7
* Oops. Didn't mean to leave this in.Evan Cheng2007-10-051-1/+0
* If a node that defines a physical register that is expensive to copy. TheEvan Cheng2007-10-051-19/+132
* If two instructions are both two-address code, favors (schedule closer toEvan Cheng2007-09-281-3/+20
* Remove a poor scheduling heuristic.Evan Cheng2007-09-281-34/+5
* Trim some unneeded fields.Evan Cheng2007-09-281-17/+8
* Avoid inserting a live register more than once.Evan Cheng2007-09-271-8/+18
* Boogs.Evan Cheng2007-09-271-10/+10
* Be smarter about which node to force schedule. Reduce # of duplications + cop...Evan Cheng2007-09-271-84/+120
* Backtracking only when it won't create a cycle.Evan Cheng2007-09-271-23/+35
* - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo.Evan Cheng2007-09-261-65/+145
* Added major new capabilities to scheduler (only BURR for now) to support phys...Evan Cheng2007-09-251-71/+398
* Use struct SDep instead of std::pair for SUnit pred and succ lists. First stepEvan Cheng2007-09-191-22/+22
* Bug fixes.Evan Cheng2007-09-131-4/+4
* Minor cleanups to reduce some spurious differences between differentDan Gohman2007-08-201-9/+11
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-181-0/+944
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