| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 2013-01-02 | 1 | -2/+2 |
| * | Change TargetLowering::getRepRegClassFor to take an MVT, instead of | Patrik Hagglund | 2012-12-13 | 1 | -8/+8 |
| * | Revert EVT->MVT changes, r169836-169851, due to buildbot failures. | Patrik Hagglund | 2012-12-11 | 1 | -8/+8 |
| * | Change TargetLowering::getRepRegClassFor to take an MVT, instead of | Patrik Hagglund | 2012-12-11 | 1 | -8/+8 |
| * | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 2012-12-03 | 1 | -10/+10 |
| * | misched: Infrastructure for weak DAG edges. | Andrew Trick | 2012-11-12 | 1 | -1/+1 |
| * | ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies. | Andrew Trick | 2012-11-06 | 1 | -22/+14 |
| * | Move TargetData to DataLayout. | Micah Villmow | 2012-10-08 | 1 | -1/+1 |
| * | Release build: guard dump functions with | Manman Ren | 2012-09-11 | 1 | -2/+2 |
| * | Release build: guard dump functions with "ifndef NDEBUG" | Manman Ren | 2012-09-06 | 1 | -0/+4 |
| * | Add a new optimization pass: Stack Coloring, that merges disjoint static allo... | Nadav Rotem | 2012-09-06 | 1 | -0/+2 |
| * | Fix a typo (the the => the) | Sylvestre Ledru | 2012-07-23 | 1 | -1/+1 |
| * | sdsched: Use the right heuristics when -mcpu is not provided and we have no i... | Andrew Trick | 2012-06-05 | 1 | -13/+12 |
| * | Switch all register list clients to the new MC*Iterator interface. | Jakob Stoklund Olesen | 2012-06-01 | 1 | -1/+1 |
| * | Mark some static arrays as const. | Craig Topper | 2012-05-24 | 1 | -1/+1 |
| * | Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). | Jakob Stoklund Olesen | 2012-05-07 | 1 | -5/+6 |
| * | Source order scheduler should not preschedule nodes with multiple uses. rdar:... | Evan Cheng | 2012-03-22 | 1 | -7/+11 |
| * | Use uint16_t to store instruction implicit uses and defs. Reduces static data. | Craig Topper | 2012-03-08 | 1 | -6/+6 |
| * | misched preparation: rename core scheduler methods for consistency. | Andrew Trick | 2012-03-07 | 1 | -12/+12 |
| * | misched preparation: modularize schedule printing. | Andrew Trick | 2012-03-07 | 1 | -0/+6 |
| * | misched preparation: modularize schedule verification. | Andrew Trick | 2012-03-07 | 1 | -1/+1 |
| * | Use uint16_t to store register overlaps to reduce static data. | Craig Topper | 2012-03-04 | 1 | -1/+1 |
| * | Add register mask support to ScheduleDAGRRList. | Jakob Stoklund Olesen | 2012-02-13 | 1 | -11/+49 |
| * | Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://p... | Eli Friedman | 2011-12-07 | 1 | -1/+8 |
| * | Fix an assertion in the scheduler. PR11386. No testcase included because it... | Eli Friedman | 2011-12-07 | 1 | -3/+2 |
| * | These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me | Nick Lewycky | 2011-12-07 | 1 | -66/+12 |
| * | Rename MVT::untyped to MVT::Untyped to match similar nomenclature. | Owen Anderson | 2011-11-16 | 1 | -2/+2 |
| * | Added custom lowering for load->dec->store sequence in x86 when the EFLAGS re... | Pete Cooper | 2011-11-15 | 1 | -0/+5 |
| * | Use a bigger hammer to fix PR11314 by disabling the "forcing two-address | Evan Cheng | 2011-11-10 | 1 | -1/+5 |
| * | Speculatively revert commit 144124 (djg) in the hope that the 32 bit | Duncan Sands | 2011-11-09 | 1 | -13/+3 |
| * | Add a hack to the scheduler to disable pseudo-two-address dependencies in | Dan Gohman | 2011-11-08 | 1 | -3/+13 |
| * | Reapply r143206, with fixes. Disallow physical register lifetimes | Dan Gohman | 2011-11-03 | 1 | -2/+181 |
| * | Revert r143206, as there are still some failing tests. | Dan Gohman | 2011-10-29 | 1 | -163/+2 |
| * | Reapply r143177 and r143179 (reverting r143188), with scheduler | Dan Gohman | 2011-10-28 | 1 | -2/+163 |
| * | Speculatively disable Dan's commits 143177 and 143179 to see if | Duncan Sands | 2011-10-28 | 1 | -134/+0 |
| * | Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW | Dan Gohman | 2011-10-28 | 1 | -0/+134 |
| * | Change this overloaded use of Sched::Latency to be an overloaded | Dan Gohman | 2011-10-24 | 1 | -4/+4 |
| * | Remove a now dead function, fixing -Wunused-function warnings from | Chandler Carruth | 2011-10-21 | 1 | -20/+0 |
| * | Delete the list-tdrr scheduler. Top-down schedulers are going away | Dan Gohman | 2011-10-20 | 1 | -203/+11 |
| * | PreRA scheduler should avoid cloning compares. | Andrew Trick | 2011-09-01 | 1 | -1/+35 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -20/+20 |
| * | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 2011-06-27 | 1 | -1/+1 |
| * | pre-RA-sched: Cleanup register pressure tracking. | Andrew Trick | 2011-06-27 | 1 | -7/+3 |
| * | Distinguish early clobber output operands from clobbered registers. | Jakob Stoklund Olesen | 2011-06-27 | 1 | -1/+2 |
| * | Fix some trailing issues from my introduction of MVT::untyped and its use for... | Owen Anderson | 2011-06-21 | 1 | -1/+11 |
| * | Remove unused but set variables. | Benjamin Kramer | 2011-06-18 | 1 | -2/+0 |
| * | Add a new MVT::untyped. This will be used in future work for modelling ISA f... | Owen Anderson | 2011-06-15 | 1 | -9/+39 |
| * | Added -stress-sched flag in the Asserts build. | Andrew Trick | 2011-06-15 | 1 | -14/+42 |
| * | Remove a temporary test case probe in CheckForLiveRegDef. | Andrew Trick | 2011-06-08 | 1 | -1/+0 |
| * | Fix a merge bug in preRAsched for handling physreg aliases. | Andrew Trick | 2011-06-07 | 1 | -4/+6 |
