| Commit message (Expand) | Author | Age | Files | Lines |
* | One mundane change: Change ReplaceAllUsesOfValueWith to *optionally* | Chris Lattner | 2007-10-15 | 1 | -4/+2 |
* | EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like | Evan Cheng | 2007-10-12 | 1 | -0/+13 |
* | Fix a typo in a comment. | Dan Gohman | 2007-10-05 | 1 | -1/+1 |
* | Chain producing nodes cannot be moved, not chain reading nodes. | Evan Cheng | 2007-10-05 | 1 | -5/+7 |
* | Oops. Didn't mean to leave this in. | Evan Cheng | 2007-10-05 | 1 | -1/+0 |
* | If a node that defines a physical register that is expensive to copy. The | Evan Cheng | 2007-10-05 | 1 | -19/+132 |
* | If two instructions are both two-address code, favors (schedule closer to | Evan Cheng | 2007-09-28 | 1 | -3/+20 |
* | Remove a poor scheduling heuristic. | Evan Cheng | 2007-09-28 | 1 | -34/+5 |
* | Trim some unneeded fields. | Evan Cheng | 2007-09-28 | 1 | -17/+8 |
* | Avoid inserting a live register more than once. | Evan Cheng | 2007-09-27 | 1 | -8/+18 |
* | Boogs. | Evan Cheng | 2007-09-27 | 1 | -10/+10 |
* | Be smarter about which node to force schedule. Reduce # of duplications + cop... | Evan Cheng | 2007-09-27 | 1 | -84/+120 |
* | Backtracking only when it won't create a cycle. | Evan Cheng | 2007-09-27 | 1 | -23/+35 |
* | - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo. | Evan Cheng | 2007-09-26 | 1 | -65/+145 |
* | Added major new capabilities to scheduler (only BURR for now) to support phys... | Evan Cheng | 2007-09-25 | 1 | -71/+398 |
* | Use struct SDep instead of std::pair for SUnit pred and succ lists. First step | Evan Cheng | 2007-09-19 | 1 | -22/+22 |
* | Bug fixes. | Evan Cheng | 2007-09-13 | 1 | -4/+4 |
* | Minor cleanups to reduce some spurious differences between different | Dan Gohman | 2007-08-20 | 1 | -9/+11 |
* | It's not necessary to do rounding for alloca operations when the requested | Dan Gohman | 2007-07-18 | 1 | -0/+944 |