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* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-021-0/+4
* Add comments.Evan Cheng2011-04-011-2/+4
* Assign node order numbers to results of call instruction lowering. This shoul...Evan Cheng2011-04-011-4/+8
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-012-19/+154
* Turn SelectionDAGBuilder::GetRegistersForValue into a local function.Benjamin Kramer2011-03-262-19/+16
* Fix for -pre-RA-sched=source.Andrew Trick2011-03-251-0/+2
* PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.Eli Friedman2011-03-232-60/+30
* Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick2011-03-231-0/+9
* whitespaceAndrew Trick2011-03-231-2/+2
* Added block number and name to isel debug output.Andrew Trick2011-03-231-12/+25
* Grammar-o.Eric Christopher2011-03-211-1/+1
* Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem2011-03-191-1/+48
* BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied...Benjamin Kramer2011-03-171-9/+22
* Move more logic into getTypeForExtArgOrReturn.Cameron Zwarich2011-03-171-6/+2
* Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().Cameron Zwarich2011-03-171-1/+1
* The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byteCameron Zwarich2011-03-161-5/+2
* Don't recompute something that we already have in a local variable.Cameron Zwarich2011-03-161-2/+2
* sext(undef) = 0, because the top bits will all be the same.Evan Cheng2011-03-151-1/+5
* BIT_CONVERT has been renamed to BITCAST.Evan Cheng2011-03-141-1/+1
* Minor optimization. sign-ext/anyext of undef is still undef.Evan Cheng2011-03-141-0/+4
* Teach FastISel to support register-immediate-immediate instructions.Owen Anderson2011-03-111-0/+23
* Replace -dag-chain-limit flag with constant. It has survived a release cycle ...Andrew Trick2011-03-111-3/+1
* Avoid replacing the value of a directly stored load with the stored value if ...Evan Cheng2011-03-111-2/+1
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-102-10/+23
* Revert 127368 and 127371 for now.Evan Cheng2011-03-092-23/+10
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-092-10/+23
* Improve pre-RA-sched register pressure tracking for duplicate operands.Andrew Trick2011-03-091-1/+5
* Fix typo, make helper static.Benjamin Kramer2011-03-091-3/+3
* Fix some latent bugs if the nodes are unschedulable. We'd gotten awayEric Christopher2011-03-082-1/+10
* Further improvements to pre-RA-sched=list-ilp.Andrew Trick2011-03-081-17/+62
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-1/+1
* Use the correct LHS type when determining the legalization of a shift's RHS t...Owen Anderson2011-03-072-5/+8
* Typo.Eric Christopher2011-03-061-1/+1
* Disable a couple of experimental heuristics to get the best results from the ...Andrew Trick2011-03-061-2/+2
* Be explicit with abs(). Visual Studio workaround.Andrew Trick2011-03-051-4/+6
* Fix for -sched-high-latency-cycles in sched=list-ilp mode.Andrew Trick2011-03-051-1/+3
* Missing comment.Andrew Trick2011-03-051-0/+2
* Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick2011-03-052-23/+156
* Revert commit 126684 "Use the correct shift amount type". It is only the cor...Duncan Sands2011-03-041-1/+1
* Minor pre-RA-sched fixes and cleanup.Andrew Trick2011-03-041-7/+15
* There are times when the landing pad won't have a call to 'eh.selector' inBill Wendling2011-03-031-9/+23
* Revert r123908; the code in question is completely untested and wrong.Eli Friedman2011-03-032-28/+0
* Avoid exponential blow-up when printing DAGs.Bob Wilson2011-03-021-2/+5
* Can't introduce floating-point immediate constants after legalization.Stuart Hastings2011-03-021-2/+6
* Add a few missed unary cases when legalizing vector results. Put some casesDuncan Sands2011-03-011-31/+43
* trailing whitespace.Jim Grosbach2011-03-011-1/+1
* Generalize the register matching code in DAGISel a bit.Jim Grosbach2011-03-011-0/+12
* Use the correct shift amount type.Owen Anderson2011-02-281-1/+1
* Clean whitespace.Owen Anderson2011-02-281-3/+3
* Legalize support for fpextend of vector. PR9309.Duncan Sands2011-02-271-0/+2
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