| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Merge upstream to r133240 at Fri. 17th Jun 2011. | Nowar Gu | 2011-06-20 | 18 | -1079/+2137 |
| |\ |
|
| | * | Don't use register classes larger than TLI->getRegClassFor(VT). | Jakob Stoklund Olesen | 2011-06-16 | 1 | -2/+7 |
| | * | Introduce MachineBranchProbabilityInfo class, which has similar API to | Jakub Staszak | 2011-06-16 | 3 | -11/+50 |
| | * | Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi... | Owen Anderson | 2011-06-16 | 1 | -5/+6 |
| | * | Add TargetRegisterInfo::getRawAllocationOrder(). | Jakob Stoklund Olesen | 2011-06-16 | 1 | -9/+16 |
| | * | Add a DAGCombine for (ext (binop (load x), cst)). | Nick Lewycky | 2011-06-16 | 1 | -61/+109 |
| | * | Add a new MVT::untyped. This will be used in future work for modelling ISA f... | Owen Anderson | 2011-06-15 | 2 | -9/+47 |
| | * | Added -stress-sched flag in the Asserts build. | Andrew Trick | 2011-06-15 | 2 | -15/+43 |
| | * | getZeroExtendInReg needs to get a scalar type | Nadav Rotem | 2011-06-15 | 1 | -1/+2 |
| | * | Enable the simplification of truncating-store after fixing the usage of | Nadav Rotem | 2011-06-15 | 2 | -4/+5 |
| | * | When pattern matching during instruction selection make sure shl x,1 is not | Chad Rosier | 2011-06-14 | 1 | -0/+3 |
| | * | Add a testcase for checking the integer-promotion of many different vector | Nadav Rotem | 2011-06-14 | 2 | -2/+171 |
| | * | Disable trunc-store simplification on vectors. | Nadav Rotem | 2011-06-14 | 1 | -1/+1 |
| | * | Add one more argument to the prefetch intrinsic to indicate whether it's a data | Bruno Cardoso Lopes | 2011-06-14 | 1 | -2/+3 |
| | * | Fix a bug in FindMemType. When widening vector loads, use a wider memory type | Nadav Rotem | 2011-06-13 | 1 | -0/+2 |
| | * | Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd | Nadav Rotem | 2011-06-12 | 1 | -5/+17 |
| | * | Improve the generated code by getCopyFromPartsVector for promoted integer types. | Nadav Rotem | 2011-06-12 | 1 | -21/+20 |
| | * | Revert r132871. | Chad Rosier | 2011-06-11 | 1 | -1/+1 |
| | * | Typo. | Chad Rosier | 2011-06-11 | 1 | -1/+1 |
| | * | 80-col cleanups. | Eric Christopher | 2011-06-10 | 1 | -6/+5 |
| | * | Change this DAGCombine to build AND of SHR instead of SHR of AND; this matche... | Eli Friedman | 2011-06-09 | 1 | -15/+16 |
| | * | Add a parameter to CCState so that it can access the MachineFunction. | Eric Christopher | 2011-06-08 | 2 | -8/+11 |
| | * | Remove a temporary test case probe in CheckForLiveRegDef. | Andrew Trick | 2011-06-08 | 1 | -1/+0 |
| | * | Fix a merge bug in preRAsched for handling physreg aliases. | Andrew Trick | 2011-06-07 | 1 | -4/+6 |
| | * | Add methods to support the integer-promotion of vector types. Methods to | Nadav Rotem | 2011-06-06 | 3 | -0/+192 |
| | * | Avoid FGETSIGN of 80-bit types. Fixes PR10085. | Stuart Hastings | 2011-06-06 | 1 | -6/+8 |
| | * | PR10077: fix fast-isel of extractvalue of aggregate constants. | Eli Friedman | 2011-06-06 | 1 | -1/+3 |
| | * | TypeLegalizer: Add support for passing of vector-promoted types in registers ... | Nadav Rotem | 2011-06-04 | 1 | -2/+40 |
| | * | TypeLegalizer: Fix a bug in the promotion of elements of integer vectors. | Nadav Rotem | 2011-06-04 | 1 | -16/+22 |
| | * | Add a TODO about memory operands. | Eric Christopher | 2011-06-03 | 1 | -1/+5 |
| | * | Have LowerOperandForConstraint handle multiple character constraints. | Eric Christopher | 2011-06-02 | 2 | -3/+7 |
| | * | Revert 132424 to fix PR10068. | Rafael Espindola | 2011-06-02 | 1 | -5/+4 |
| | * | Use TRI::has{Sub,Super}ClassEq() where possible. | Jakob Stoklund Olesen | 2011-06-02 | 1 | -1/+1 |
| | * | Recommit 132404 with fixes. rdar://problem/5993888 | Stuart Hastings | 2011-06-01 | 1 | -4/+5 |
| | * | Allow bitcasts between valid types of the same size and vector | Eric Christopher | 2011-06-01 | 1 | -0/+6 |
| | * | Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use | Nadav Rotem | 2011-06-01 | 5 | -96/+71 |
| | * | Fix double FGETSIGN to work on x86_32; followup to 132396. | Stuart Hastings | 2011-06-01 | 1 | -3/+6 |
| | * | Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695 | Stuart Hastings | 2011-06-01 | 1 | -6/+2 |
| | * | This patch is another step in the direction of adding vector select. In this | Nadav Rotem | 2011-06-01 | 1 | -1/+28 |
| | * | Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTy... | Nadav Rotem | 2011-05-28 | 2 | -33/+26 |
| | * | Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' | Nadav Rotem | 2011-05-27 | 3 | -4/+4 |
| | * | Rewrite fast-isel integer cast handling to handle more cases, and to be simpl... | Eli Friedman | 2011-05-25 | 1 | -26/+6 |
| | * | Remove unused statistical counter. | Devang Patel | 2011-05-25 | 1 | -57/+0 |
| | * | Remove dead code. | Devang Patel | 2011-05-24 | 1 | -10/+0 |
| | * | - Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is | Evan Cheng | 2011-05-24 | 1 | -5/+13 |
| | * | Revert 121907 (it causes llc crash) and apply original patch from PR9817. | Devang Patel | 2011-05-23 | 2 | -3/+3 |
| | * | Preserve debug info during iSel by keeping DanglingDebugInfoMap live until en... | Devang Patel | 2011-05-23 | 3 | -1/+19 |
| | * | While replacing all uses of a SDValue with another value, do not forget to tr... | Devang Patel | 2011-05-23 | 1 | -0/+3 |
| | * | Eliminate some temporary variables, and don't call getByValTypeAlignment | Chris Lattner | 2011-05-22 | 1 | -6/+8 |
| | * | Implement mulo x, 2 -> addo x, x in DAGCombiner. | Benjamin Kramer | 2011-05-21 | 1 | -0/+24 |
