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* typo (4th checkin for one fix)Andrew Trick2010-11-121-1/+1
* Fixes PR8287: SD scheduling time. The fix is a failsafe that preventsAndrew Trick2010-11-121-13/+53
* tidy up.Chris Lattner2010-11-121-7/+5
* Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this.Dan Gohman2010-11-111-14/+0
* Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shlDan Gohman2010-11-091-0/+1
* Fix an inline asm pasto from 117667; was preventingDale Johannesen2010-11-091-1/+2
* When passing a parameter using the 'byval' mechanism, inline code needs to be...Duncan Sands2010-11-051-0/+2
* Just return undef for invalid masks or elts, and since we're doing that,Eric Christopher2010-11-031-5/+6
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-032-7/+5
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-3/+3
* If we have an undef mask our Elt will be -1 for our access, handleEric Christopher2010-11-031-3/+7
* Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman2010-11-031-1/+36
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-032-4/+15
* If value map does not have register for an argument then try to find frame in...Devang Patel2010-11-021-5/+8
* Use frameindex, if available, as a last resort to emit debug info for a param...Devang Patel2010-11-021-2/+13
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-5/+0
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-292-24/+78
* Inline asm multiple alternative constraints development phase 2 - improved ba...John Thompson2010-10-292-46/+76
* Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson2010-10-281-24/+28
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-0/+3
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng2010-10-281-3/+0
* Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng2010-10-281-0/+3
* Use a MemIntrinsicSDNode for ISD::PREFETCH, which touchesDale Johannesen2010-10-262-2/+11
* Assign source ordering to nodes created for StoreInst.Devang Patel2010-10-261-2/+5
* For statistics that are only used in functions declared in !NDEBUG, wrap theNick Lewycky2010-10-261-0/+3
* Simplify.Devang Patel2010-10-251-9/+9
* Add counters to count basic blocks and machine basic blocks with out of order...Devang Patel2010-10-251-4/+63
* Move the remaining attribute macros to systematic names based on the attributeChandler Carruth2010-10-231-12/+12
* X86: Base _fltused on the FunctionType of the called value instead of the pot...Michael J. Spencer2010-10-211-19/+20
* CodeGen-Windows: Only emit _fltused if a VarArg function is called with float...Michael J. Spencer2010-10-211-5/+5
* Remove Synthesizable from the Type system; as MMX vectorDale Johannesen2010-10-202-11/+11
* Make CodeGen TBAA-aware.Dan Gohman2010-10-203-21/+42
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-193-2/+13
* Get rid of static constructors for pass registration. Instead, every pass ex...Owen Anderson2010-10-191-2/+4
* X86-Windows: Emit an undefined global __fltused symbol when targeting WindowsMichael J. Spencer2010-10-161-0/+20
* Whitespace!Michael J. Spencer2010-10-161-46/+46
* fix the default va_arg expansion (in the realignment case) to not implicitlyChris Lattner2010-10-101-1/+1
* ComputeLinearIndex doesn't need its TLI argument.Dan Gohman2010-10-061-4/+2
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-19/+1
* Use a more efficient lowering of uint64_t --> float that can take advantage o...Owen Anderson2010-10-051-6/+28
* This DAG combine BRCOND transformation can look pass truncate of the operand:Evan Cheng2010-10-041-13/+18
* Fix code gen crash reported in PR 8235. We still lose debug info for the unus...Devang Patel2010-10-011-0/+3
* typoGabor Greif2010-10-011-1/+1
* fix typoChris Lattner2010-10-011-1/+1
* fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350Chris Lattner2010-10-011-0/+9
* Massive rewrite of MMX: Dale Johannesen2010-09-301-0/+60
* When isel is emitting instructions for an x86 target without CMOV, the CFG isJakob Stoklund Olesen2010-09-303-1/+24
* Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng2010-09-291-17/+17
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
* Don't try to make a vector of x86mmx; this won't work,Dale Johannesen2010-09-271-2/+4