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* The scheduler needs to be aware on the existence of untyped nodes when it per...Owen Anderson2011-06-241-1/+2
* Handle debug info for i128 constants.Devang Patel2011-06-242-9/+10
* Replace the existing forms of ConstantArray::get() with a single formJay Foad2011-06-221-1/+1
* Fix some trailing issues from my introduction of MVT::untyped and its use for...Owen Anderson2011-06-211-1/+11
* Teach dag combine to match halfword byteswap patterns.Evan Cheng2011-06-211-2/+264
* Fix PromoteIntRes_TRUNCATE: Add support for cases where theNadav Rotem2011-06-201-4/+28
* Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve vect...Nadav Rotem2011-06-191-7/+5
* Calls to AssertZext and getZeroExtendInReg must be made using scalar types.Nadav Rotem2011-06-191-3/+4
* When promoting the vector elements in CopyToParts, use vector truncNadav Rotem2011-06-191-11/+3
* Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.Benjamin Kramer2011-06-182-4/+4
* Remove unused but set variables.Benjamin Kramer2011-06-182-19/+4
* Fix UMULO support for 2x register width to allow the fullEric Christopher2011-06-181-0/+21
* Fix comment.Eric Christopher2011-06-171-2/+1
* Lower multiply with overflow checking to __mulo<mode>Eric Christopher2011-06-173-4/+71
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-161-2/+7
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-163-11/+50
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi...Owen Anderson2011-06-161-5/+6
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-161-9/+16
* Add a DAGCombine for (ext (binop (load x), cst)).Nick Lewycky2011-06-161-61/+109
* Add a new MVT::untyped. This will be used in future work for modelling ISA f...Owen Anderson2011-06-152-9/+47
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-152-15/+43
* getZeroExtendInReg needs to get a scalar typeNadav Rotem2011-06-151-1/+2
* Enable the simplification of truncating-store after fixing the usage ofNadav Rotem2011-06-152-4/+5
* When pattern matching during instruction selection make sure shl x,1 is notChad Rosier2011-06-141-0/+3
* Add a testcase for checking the integer-promotion of many different vectorNadav Rotem2011-06-142-2/+171
* Disable trunc-store simplification on vectors.Nadav Rotem2011-06-141-1/+1
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-2/+3
* Fix a bug in FindMemType. When widening vector loads, use a wider memory typeNadav Rotem2011-06-131-0/+2
* Fix a bug in the calculation of the vectorTypeBreakdown into registers. OddNadav Rotem2011-06-121-5/+17
* Improve the generated code by getCopyFromPartsVector for promoted integer types.Nadav Rotem2011-06-121-21/+20
* Revert r132871.Chad Rosier2011-06-111-1/+1
* Typo.Chad Rosier2011-06-111-1/+1
* 80-col cleanups.Eric Christopher2011-06-101-6/+5
* Change this DAGCombine to build AND of SHR instead of SHR of AND; this matche...Eli Friedman2011-06-091-15/+16
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-082-8/+11
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
* Add methods to support the integer-promotion of vector types. Methods toNadav Rotem2011-06-063-0/+192
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
* PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman2011-06-061-1/+3
* TypeLegalizer: Add support for passing of vector-promoted types in registers ...Nadav Rotem2011-06-041-2/+40
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
* Add a TODO about memory operands.Eric Christopher2011-06-031-1/+5
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-022-3/+7
* Revert 132424 to fix PR10068.Rafael Espindola2011-06-021-5/+4
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-1/+1
* Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings2011-06-011-4/+5
* Allow bitcasts between valid types of the same size and vectorEric Christopher2011-06-011-0/+6
* Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer useNadav Rotem2011-06-015-96/+71
* Fix double FGETSIGN to work on x86_32; followup to 132396.Stuart Hastings2011-06-011-3/+6
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