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path: root/lib/CodeGen/VirtRegRewriter.cpp
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* More migration to raw_ostream, the water has dried up around the iostream hole.Daniel Dunbar2009-07-251-5/+7
* Let each target determines whether a machine instruction is dead. If true, th...Evan Cheng2009-07-221-25/+2
* Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegFo...Evan Cheng2009-07-211-23/+27
* Enable cross register class coalescing.Evan Cheng2009-07-181-4/+35
* Fix my brain cramp by inverting the assertion condition.Evan Cheng2009-07-171-3/+1
* Disable this assert for now, it is firing on an llvm-gcc bootstrap. :(Daniel Dunbar2009-07-161-0/+2
* Fix inverted preprocessor conditional.Daniel Dunbar2009-07-161-1/+1
* Changed my mind. We now allow remat of instructions whose defs have subreg in...Evan Cheng2009-07-161-1/+8
* Let callers decide the sub-register index on the def operand of rematerialize...Evan Cheng2009-07-161-1/+1
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Edwin Török2009-07-141-4/+4
* assert(0) -> LLVM_UNREACHABLE.Edwin Török2009-07-111-4/+5
* Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpInd...Evan Cheng2009-07-101-1/+27
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the...Evan Cheng2009-07-011-2/+6
* Add a bit IsUndef to MachineOperand. This indicates the def / use register op...Evan Cheng2009-06-301-26/+22
* Removed SimpleRewriter.Lang Hames2009-06-041-82/+2
* Fix for PR4225: When rewriter reuse a value in a physical register , it clear...Evan Cheng2009-06-031-5/+19
* Update to in-place spilling framework. Includes live interval scaling and tri...Lang Hames2009-06-021-3/+42
* Fix PR4210. Rewritter should track and update kills of sub-registers as well.Evan Cheng2009-05-151-42/+63
* Teach TransferDeadness to delete truly dead instructions if they do not produ...Evan Cheng2009-05-121-13/+37
* Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.Lang Hames2009-05-061-0/+2141
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