aboutsummaryrefslogtreecommitdiffstats
path: root/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* support > 4G stack objectsChris Lattner2007-04-252-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36422 91177308-0d34-0410-b5e6-96231b3b80d8
* allow support for 64-bit stack objectsChris Lattner2007-04-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36420 91177308-0d34-0410-b5e6-96231b3b80d8
* Be more careful about folding op(x, undef) when we have vector operands.Chris Lattner2007-04-251-9/+16
| | | | | | | This fixes CodeGen/X86/2007-04-24-VectorCrash.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36413 91177308-0d34-0410-b5e6-96231b3b80d8
* Assertion when using a 1-element vector for an add operation. Get theBill Wendling2007-04-241-4/+7
| | | | | | | real vector type in this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8
* Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings aboutScott Michel2007-04-241-2/+2
| | | | | | | tests always being true in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36387 91177308-0d34-0410-b5e6-96231b3b80d8
* modify per review commentaryDale Johannesen2007-04-231-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36383 91177308-0d34-0410-b5e6-96231b3b80d8
* make EmitAlignment work the way Chris says it shouldDale Johannesen2007-04-231-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36368 91177308-0d34-0410-b5e6-96231b3b80d8
* PR400 phase 2. Propagate attributed load/store information through DAGs.Christopher Lamb2007-04-223-36/+112
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36356 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 TLS: Implement review feedback.Lauro Ramos Venancio2007-04-211-1/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36318 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert Christopher Lamb's load/store alignment changes.Reid Spencer2007-04-213-79/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36309 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for alignment attributes on load/store instructionsChristopher Lamb2007-04-213-36/+79
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36301 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.Lauro Ramos Venancio2007-04-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36290 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-202-2/+22
| | | | | | | X86 32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
* VarInfo::UsedBlocks is no longer used. Remove.Evan Cheng2007-04-184-17/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36250 91177308-0d34-0410-b5e6-96231b3b80d8
* allow SRL to simplify its operands, as it doesn't demand all bits as input.Chris Lattner2007-04-181-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
* When replacing a node in SimplifyDemandedBits, if the old node used anyChris Lattner2007-04-181-1/+8
| | | | | | | | single-use nodes, they will be dead soon. Make sure to remove them before processing other nodes. This implements CodeGen/X86/shl_elim.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36244 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a pastoChris Lattner2007-04-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36242 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't populate TryAgainList when coalescing only physical registers with ↵Evan Cheng2007-04-181-6/+6
| | | | | | virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36240 91177308-0d34-0410-b5e6-96231b3b80d8
* Increment use count of new virtuals created during PHI elimination.Evan Cheng2007-04-181-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36233 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in my previous patch, grabbing the shift amount width from theChris Lattner2007-04-171-2/+2
| | | | | | | wrong operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.Chris Lattner2007-04-171-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36221 91177308-0d34-0410-b5e6-96231b3b80d8
* Copy coalescing change to prevent a physical register from being pin to aEvan Cheng2007-04-172-86/+98
| | | | | | | | | | | | | | long live interval that has low usage density. 1. Change order of coalescing to join physical registers with virtual registers first before virtual register intervals become too long. 2. Check size and usage density to determine if it's worthwhile to join. 3. If joining is aborted, assign virtual register live interval allocation preference field to the physical register. 4. Register allocator should try to allocate to the preferred register first (if available) to create identify moves that can be eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36218 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a register allocation preference field; add a method to compute size of ↵Evan Cheng2007-04-171-0/+9
| | | | | | a live interval. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36216 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep track of number of uses within the function per virtual register.Evan Cheng2007-04-171-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36214 91177308-0d34-0410-b5e6-96231b3b80d8
* SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBitsChris Lattner2007-04-171-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | a chance to hack on it. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr instead of: _baz: srwi r2, r4, 24 rlwimi r2, r3, 8, 0, 23 srwi r2, r2, 9 extsh r3, r2 blr This implements CodeGen/PowerPC/sign_ext_inreg1.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix problems in the PartSet lowering having to do with incorrect bit width.Reid Spencer2007-04-161-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36180 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-164-47/+47
| | | | | | | target for tabs checking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
* disable switch lowering using shift/and. It still breaks ppc bootstrap forChris Lattner2007-04-141-0/+1
| | | | | | | some reason. :( Will investigate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36011 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR1325: Case range optimization was performed in the case itAnton Korobeynikov2007-04-141-4/+2
| | | | | | | shouldn't. Also fix some "latent" bug on 64-bit platforms git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35990 91177308-0d34-0410-b5e6-96231b3b80d8
* disable shift/and lowering to work around PR1325 for now.Chris Lattner2007-04-141-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35985 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR1323 : we haven't updated phi nodes in good manner :)Anton Korobeynikov2007-04-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35963 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure intrinsics that are lowered to functions make the function weakReid Spencer2007-04-121-2/+2
| | | | | | | | linkage so we only end up with one of them in a program. These are, after all overloaded and templatish in nature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35956 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bugs in generated code for part_select and part_set so that llc doesn'tReid Spencer2007-04-121-35/+44
| | | | | | | barf when CBE is run with a program that contains these intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35946 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in PartSet. The replacement value needs to be zext or trunc toReid Spencer2007-04-121-3/+7
| | | | | | | the size of the value, not just zext. Also, give better names to two BBs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35945 91177308-0d34-0410-b5e6-96231b3b80d8
* the result of an inline asm copy can be an arbitrary VT that the registerChris Lattner2007-04-121-4/+21
| | | | | | | | | class supports. In the case of vectors, this means we often get the wrong type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35944 91177308-0d34-0410-b5e6-96231b3b80d8
* fold noop vbitconvert instructionsChris Lattner2007-04-121-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35943 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix weirdness handling single element vectors.Chris Lattner2007-04-121-5/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35941 91177308-0d34-0410-b5e6-96231b3b80d8
* For PR1284:Reid Spencer2007-04-122-12/+199
| | | | | | | Implement the "part_set" intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35938 91177308-0d34-0410-b5e6-96231b3b80d8
* fix an infinite loop compiling ldecod, notice by JeffC.Chris Lattner2007-04-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35910 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix this harder.Chris Lattner2007-04-111-12/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35888 91177308-0d34-0410-b5e6-96231b3b80d8
* don't create shifts by zero, fix some problems with my previous patchChris Lattner2007-04-111-3/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35887 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which oftenChris Lattner2007-04-111-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allows other simplifications. For example, this compiles: int isnegative(unsigned int X) { return !(X < 2147483648U); } Into this code: x86: movl 4(%esp), %eax shrl $31, %eax ret arm: mov r0, r0, lsr #31 bx lr thumb: lsr r0, r0, #31 bx lr instead of: x86: cmpl $0, 4(%esp) sets %al movzbl %al, %eax ret arm: mov r3, #0 cmp r0, #0 movlt r3, #1 mov r0, r3 bx lr thumb: mov r2, #1 mov r1, #0 cmp r0, #0 blt LBB1_2 @entry LBB1_1: @entry cpy r2, r1 LBB1_2: @entry cpy r0, r2 bx lr Testcase here: test/CodeGen/Generic/ispositive.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35883 91177308-0d34-0410-b5e6-96231b3b80d8
* Codegen integer abs more efficiently using the trick from the PPC CWG. ThisChris Lattner2007-04-111-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll X86 Old: X86 New: _test: _test: movl 4(%esp), %ecx movl 4(%esp), %eax movl %ecx, %eax movl %eax, %ecx negl %eax sarl $31, %ecx testl %ecx, %ecx addl %ecx, %eax cmovns %ecx, %eax xorl %ecx, %eax ret ret PPC Old: PPC New: _test: _test: cmpwi cr0, r3, -1 srawi r2, r3, 31 neg r2, r3 add r3, r3, r2 bgt cr0, LBB1_2 ; xor r3, r3, r2 LBB1_1: ; blr mr r3, r2 LBB1_2: ; blr ARM Old: ARM New: _test: _test: rsb r3, r0, #0 add r3, r0, r0, asr #31 cmp r0, #0 eor r0, r3, r0, asr #31 movge r3, r0 bx lr mov r0, r3 bx lr Thumb Old: Thumb New: _test: _test: neg r2, r0 asr r2, r0, #31 cmp r0, #0 add r0, r0, r2 bge LBB1_2 eor r0, r2 LBB1_1: @ bx lr cpy r0, r2 LBB1_2: @ bx lr Sparc Old: Sparc New: test: test: save -96, %o6, %o6 save -96, %o6, %o6 sethi 0, %l0 sra %i0, 31, %l0 sub %l0, %i0, %l0 add %i0, %l0, %l1 subcc %i0, -1, %l1 xor %l1, %l0, %i0 bg .BB1_2 restore %g0, %g0, %g0 nop retl .BB1_1: nop or %g0, %l0, %i0 .BB1_2: restore %g0, %g0, %g0 retl nop It also helps alpha/ia64 :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35881 91177308-0d34-0410-b5e6-96231b3b80d8
* For PR1146:Reid Spencer2007-04-111-13/+13
| | | | | | | | Put the parameter attributes in their own ParamAttr name space. Adjust the rest of llvm as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35877 91177308-0d34-0410-b5e6-96231b3b80d8
* apparently some people commit without building the tree, or they forget toChris Lattner2007-04-102-2/+2
| | | | | | | commit a LOT of files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35858 91177308-0d34-0410-b5e6-96231b3b80d8
* No longer needed.Jeff Cohen2007-04-091-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35850 91177308-0d34-0410-b5e6-96231b3b80d8
* remove dead target hooks.Chris Lattner2007-04-091-19/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35847 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some dead target hooks, subsumed by isLegalAddressingModeChris Lattner2007-04-091-17/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
* Use integer log for metric calculationAnton Korobeynikov2007-04-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35834 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak VC++ build.Jeff Cohen2007-04-091-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35817 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2024-10-28 15:34:42 +0000