| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Post-ra LICM should take care not to hoist an instruction that would clobber a | Evan Cheng | 2012-03-27 | 1 | -4/+28 |
| * | During MachineCopyPropagation a register may be the source operand of multiple | Lang Hames | 2012-03-27 | 1 | -17/+26 |
| * | Add a debug option to dump PBQP graphs during register allocation. | Lang Hames | 2012-03-26 | 1 | -0/+29 |
| * | Use the file in the inlined die rather than the compile unit for | Eric Christopher | 2012-03-26 | 1 | -1/+2 |
| * | No need to do an expensive stable sort for a bunch of integers. | Benjamin Kramer | 2012-03-26 | 1 | -3/+3 |
| * | Prune some includes and forward declarations. | Craig Topper | 2012-03-26 | 1 | -3/+4 |
| * | Add a debug statement. | Eric Christopher | 2012-03-26 | 1 | -1/+3 |
| * | Add the ability to promote legal integer VAARGs. This is required for the PPC... | Hal Finkel | 2012-03-24 | 1 | -1/+33 |
| * | Pretty-printing comments for literal floating point in .s files. | Jim Grosbach | 2012-03-23 | 1 | -2/+6 |
| * | Add support for register masks to PBQP. | Lang Hames | 2012-03-23 | 1 | -4/+38 |
| * | Source order scheduler should not preschedule nodes with multiple uses. rdar:... | Evan Cheng | 2012-03-22 | 1 | -7/+11 |
| * | Assign node orders to target intrinsics which do not produce results. rdar://... | Evan Cheng | 2012-03-22 | 1 | -0/+6 |
| * | In erroneous inline assembly we could mistakenly try to access the | Eric Christopher | 2012-03-22 | 1 | -1/+5 |
| * | [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271% | Chad Rosier | 2012-03-22 | 1 | -0/+7 |
| * | Checking a build_vector for an all-ones value. | Jim Grosbach | 2012-03-21 | 1 | -5/+14 |
| * | misched: fix LiveInterval update for bottom-up scheduling | Andrew Trick | 2012-03-21 | 1 | -3/+13 |
| * | misched: trace LiveIntervals after scheduling. | Andrew Trick | 2012-03-21 | 1 | -0/+1 |
| * | misched: obvious iterator update fixes for bottom-up. | Andrew Trick | 2012-03-21 | 1 | -0/+6 |
| * | misched: cleanup main loop | Andrew Trick | 2012-03-21 | 1 | -10/+14 |
| * | misched: fix LI update for bottom-up. | Andrew Trick | 2012-03-21 | 1 | -1/+7 |
| * | It's possible to have a constant expression who's size is quite big (e.g., | Bill Wendling | 2012-03-20 | 1 | -11/+17 |
| * | When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add user... | Craig Topper | 2012-03-20 | 1 | -0/+1 |
| * | Do everything up to generating code to try to get a register for | Eric Christopher | 2012-03-20 | 1 | -1/+6 |
| * | Untabify. | Eric Christopher | 2012-03-20 | 1 | -2/+2 |
| * | Add another debugging statement here. | Eric Christopher | 2012-03-20 | 1 | -0/+4 |
| * | Use lookUpRegForValue here instead of duplicating the code. | Eric Christopher | 2012-03-20 | 1 | -9/+2 |
| * | f16 FDIV can now be legalized by promoting to f32 | Pete Cooper | 2012-03-19 | 1 | -1/+2 |
| * | Add an option to the MI scheduler to cut off scheduling after a fixed number of | Lang Hames | 2012-03-19 | 1 | -1/+19 |
| * | Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala. | Duncan Sands | 2012-03-19 | 1 | -0/+6 |
| * | CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector. | Benjamin Kramer | 2012-03-17 | 2 | -11/+12 |
| * | MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty. | Benjamin Kramer | 2012-03-17 | 1 | -6/+2 |
| * | ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th... | Benjamin Kramer | 2012-03-16 | 1 | -2/+2 |
| * | Limit the number of memory operands in MachineInstr to 2^16 and store the num... | Benjamin Kramer | 2012-03-16 | 1 | -11/+10 |
| * | CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse the... | Benjamin Kramer | 2012-03-16 | 1 | -7/+7 |
| * | misched: add DAG edges from vreg defs to ExitSU. | Andrew Trick | 2012-03-16 | 1 | -1/+3 |
| * | Revert r152705, which reapplied r152486 as this appears to be causing failures | Chad Rosier | 2012-03-16 | 1 | -128/+34 |
| * | Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." f... | NAKAMURA Takumi | 2012-03-16 | 1 | -1/+1 |
| * | For types with a parent of the compile unit make sure and emit | Eric Christopher | 2012-03-15 | 1 | -5/+4 |
| * | We actually handle AllocaInst via getRegForValue below just fine. | Eric Christopher | 2012-03-15 | 1 | -1/+1 |
| * | Add some debugging output into fast isel as well. | Eric Christopher | 2012-03-15 | 1 | -2/+6 |
| * | Add another debug statement. | Eric Christopher | 2012-03-15 | 1 | -1/+3 |
| * | Tabs. | Eric Christopher | 2012-03-15 | 1 | -3/+3 |
| * | Typo. | Eric Christopher | 2012-03-15 | 1 | -1/+1 |
| * | When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add... | Nadav Rotem | 2012-03-15 | 1 | -0/+4 |
| * | Revert the removal of DW_AT_MIPS_linkage_name when we aren't putting | Eric Christopher | 2012-03-15 | 1 | -5/+8 |
| * | Add a xform to the DAG combiner. | Bill Wendling | 2012-03-15 | 1 | -0/+17 |
| * | Silence operator precedence warnings. | Benjamin Kramer | 2012-03-14 | 1 | -3/+3 |
| * | Reapply r152486 with a fix for the nightly testers. | Bill Wendling | 2012-03-14 | 1 | -34/+128 |
| * | Insert the debugging instructions in one fell-swoop so that it doesn't call the | Bill Wendling | 2012-03-14 | 1 | -7/+8 |
| * | misched: implemented a framework for top-down or bottom-up scheduling. | Andrew Trick | 2012-03-14 | 3 | -103/+275 |
