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* Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen2010-06-243-731/+219
* Print the LSBs of a SlotIndex symbolically using letters referring to theJakob Stoklund Olesen2010-06-241-1/+3
* Simplify this code; switch lowering shouldn't produce casesDan Gohman2010-06-241-12/+4
* Be more strict about subreg-to-subreg copies in CoalescerPair.Jakob Stoklund Olesen2010-06-241-5/+15
* Verify that VNI kills are pointing to existing instructions.Jakob Stoklund Olesen2010-06-241-0/+1
* Eliminate the other half of the BRCOND optimization, and updateDan Gohman2010-06-241-7/+0
* Eliminate the first have of the optimization which eliminates BRCONDDan Gohman2010-06-241-3/+1
* Reapply r106634, now that the bug it exposed is fixed.Dan Gohman2010-06-244-111/+50
* Optimize the "bit test" code path for switch lowering in theDan Gohman2010-06-241-15/+27
* Revert "Replace a big gob of old coalescer logic with the new CoalescerPair c...Jakob Stoklund Olesen2010-06-244-205/+544
* Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen2010-06-244-544/+205
* MorphNodeTo doesn't preserve the memory operands. Because we're morphing a nodeBill Wendling2010-06-231-0/+21
* Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner...Daniel Dunbar2010-06-234-50/+111
* Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach2010-06-232-0/+56
* Add a few VNInfo data structure checks.Jakob Stoklund Olesen2010-06-231-2/+5
* Revert r106066, "Create a more targeted fix for not sinking instructions into...Daniel Dunbar2010-06-231-14/+53
* Also convert SUBREG_TO_REG to a KILL when relevant, like the other subregJakob Stoklund Olesen2010-06-221-7/+12
* Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks outDan Gohman2010-06-223-75/+130
* Remove the SimpleJoin optimization from SimpleRegisterCoalescing.Jakob Stoklund Olesen2010-06-222-512/+68
* Use pre-increment instead of post-increment when the result is not used.Dan Gohman2010-06-222-14/+14
* When unfolding a load, avoid assuming which instruction thatDan Gohman2010-06-221-4/+18
* Use single interface, using twine, to get named metadata.Devang Patel2010-06-221-2/+2
* Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng2010-06-223-7/+23
* Discard special LLVM prefix from linkage name.Devang Patel2010-06-221-1/+2
* Do not rely on Twine temporaries to survive.Devang Patel2010-06-221-3/+4
* Fix the new load-unfolding code to update LiveVariable's dead flags,Dan Gohman2010-06-221-2/+8
* Teach two-address lowering how to unfold a load to open up commutingDan Gohman2010-06-211-0/+84
* Use A.append(...) instead of A.insert(A.end(), ...) when A is aDan Gohman2010-06-213-5/+5
* Revert r106422, which is breaking the non-fast-isel path.Dan Gohman2010-06-212-51/+11
* More changes for non-top-down fast-isel.Dan Gohman2010-06-212-11/+51
* Do one lookup instead of two.Dan Gohman2010-06-211-2/+3
* Generalize this to look in the regular ValueMap in addition toDan Gohman2010-06-211-1/+1
* Tidy.Bob Wilson2010-06-191-5/+5
* Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman2010-06-183-0/+47
* Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean upJakob Stoklund Olesen2010-06-181-2/+5
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-185-41/+57
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-182-0/+13
* TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREGJakob Stoklund Olesen2010-06-181-1/+8
* Fix an inverted condition.Evan Cheng2010-06-181-1/+1
* Fix cross initialization compilation error.Evan Cheng2010-06-181-1/+2
* Teach iff-converter to properly count # of dups. It was not skipping over dbg...Evan Cheng2010-06-181-1/+27
* Add Expand-to-libcall support for additional atomics. This covers the usualJim Grosbach2010-06-182-4/+152
* Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman2010-06-181-0/+1
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-181-2/+2
* Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,Bob Wilson2010-06-181-3/+2
* Don't bother calling releaseMemory before destroying the DominatorTreeBase.Dan Gohman2010-06-181-1/+0
* Minor code simplifications.Dan Gohman2010-06-181-18/+12
* Give NamedRegionTimer an Enabled flag, allowing all its clients toDan Gohman2010-06-183-97/+47
* Don't replace the old Ordering object with a new one; just clear()Dan Gohman2010-06-181-2/+1
* Don't call clear() on DbgInfo when it's going to be deleted anyway.Dan Gohman2010-06-181-3/+0