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path: root/lib/Target/ARM/ARM.td
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* Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more...Evan Cheng2010-08-091-0/+3
* Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).Evan Cheng2010-07-131-1/+3
* Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/packJim Grosbach2010-05-051-3/+8
* Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch byJim Grosbach2010-05-051-0/+3
* Some bits of A9 scheduling: VFPAnton Korobeynikov2010-04-071-1/+2
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-17/+1
* vml[as] are slow on 1136jf-s also.Jim Grosbach2010-04-011-1/+2
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-251-3/+10
* need to fix 'make check' tests first. revert for a moment.Jim Grosbach2010-03-251-10/+3
* switch the flag for using NEON for SP floating point to a subtarget 'feature'Jim Grosbach2010-03-251-3/+10
* switch the use-vml[as] instructions flag to a subtarget 'feature'Jim Grosbach2010-03-251-1/+10
* Add substarget feature for FP16Anton Korobeynikov2010-03-141-0/+2
* Add ARMv6 itineraries.David Goodwin2009-11-181-8/+10
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls,...Anton Korobeynikov2009-11-021-2/+6
* Remove neonfp attribute and instead set default based on CPU string. Add -arm...David Goodwin2009-10-011-4/+1
* Restore the -post-RA-scheduler flag as an override for the target specificati...David Goodwin2009-10-011-5/+1
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post...David Goodwin2009-09-301-1/+5
* Checkpoint NEON scheduling itineraries.David Goodwin2009-09-231-18/+9
* Allow a zero cycle stage to reserve/require a FU without advancing the cycle ...David Goodwin2009-08-111-1/+1
* Make NEON single-precision FP support the default for cortex-a8 (again).David Goodwin2009-08-071-1/+1
* Disable NEON single-precision FP support for Cortex-A8, for now...David Goodwin2009-08-051-1/+1
* By default, for cortex-a8 use NEON for single-precision FP. David Goodwin2009-08-051-4/+4
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ...David Goodwin2009-08-041-0/+3
* Add fake v7 itineraries for now.Evan Cheng2009-07-211-4/+6
* Add a Thumb2 instruction flag to that indicates whether the instruction can b...Evan Cheng2009-07-081-3/+3
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ...Evan Cheng2009-06-191-42/+52
* Separate V6 from V6T2 since the latter has some extra nice instructionsAnton Korobeynikov2009-06-081-2/+6
* Add placeholder for thumb2 stuffAnton Korobeynikov2009-05-291-5/+10
* Add ARMv7 architecture, Cortex processors and different FPU modes handling.Anton Korobeynikov2009-05-231-1/+10
* Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson2009-04-171-0/+2
* Move target independent td files from lib/Target/ to include/llvm/Target so t...Evan Cheng2008-11-241-1/+1
* Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 enc...Evan Cheng2008-11-061-3/+1
* Restructure ARM code emitter to use instruction formats instead of addressing...Evan Cheng2008-11-051-1/+3
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
* Initial JIT support for ARM by Raul Fernandes Herbster.Evan Cheng2007-08-071-2/+4
* Add a processor.Lauro Ramos Venancio2007-05-041-0/+1
* ARM backend contribution from Apple.Evan Cheng2007-01-191-2/+75
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-3/+0
* Remove PointerType from class TargetEvan Cheng2006-05-171-3/+0
* added a skeleton of the ARM backendRafael Espindola2006-05-141-0/+51
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