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path: root/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Use the "isCompare" machine instruction attribute instead of calling theBill Wendling2010-08-081-3/+3
* Add the Optimize Compares pass (disabled by default).Bill Wendling2010-08-061-0/+56
* Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach2010-07-301-3/+5
* prune #includes a little.Chris Lattner2010-07-201-1/+1
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-42/+0
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-217/+0
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-111-77/+36
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-091-1/+1
* For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap theBob Wilson2010-07-081-2/+2
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-061-6/+6
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-291-0/+5
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-251-0/+18
* IT instructions are considered to be scheduling hazards, but are scheduledJim Grosbach2010-06-251-1/+13
* We are missing opportunites to use ldm. Take code like this:Bill Wendling2010-06-231-0/+101
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-0/+28
* Rewrite chained if's as switches and replace assertions with llvm_unreachableBob Wilson2010-06-181-35/+55
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-9/+7
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-6/+7
* VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.Bob Wilson2010-06-151-1/+4
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-2/+2
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-2/+2
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-2/+2
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-10/+2
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-5/+5
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-1/+2
* Update the saved stack pointer in the sjlj function context following eitherJim Grosbach2010-05-271-2/+2
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-32/+32
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-0/+37
* Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.Jim Grosbach2010-05-221-0/+4
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-13/+41
* Bring back VLD1q and VST1q and use them for reloading / spilling Q registers....Evan Cheng2010-05-131-29/+69
* Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack s...Evan Cheng2010-05-071-5/+39
* Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VL...Evan Cheng2010-05-071-9/+15
* Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q...Evan Cheng2010-05-071-9/+23
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-4/+2
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coa...Evan Cheng2010-05-061-16/+35
* Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.Dan Gohman2010-05-061-4/+2
* Revert r103156 since it was breaking the build bots.Eric Christopher2010-05-061-31/+14
* Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.Evan Cheng2010-05-061-2/+4
* Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registe...Evan Cheng2010-05-061-14/+31
* Cosmetic changes.Evan Cheng2010-05-061-7/+7
* storeRegToStackSlot has forgotten about QPR_8 register class.Evan Cheng2010-05-061-1/+2
* Frame index can be negative.Evan Cheng2010-04-291-1/+1
* Add sizes non-floating point versions for the eh sjlj intrinsic expansions.Jim Grosbach2010-04-281-1/+2
* Add ARM specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+10
* Educate GetInstrSizeInBytes implementations thatDale Johannesen2010-04-071-0/+1
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-4/+4
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