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path: root/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-4/+9
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-69/+2
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+18
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-091-4/+78
* Let t2LDRBi8 and t2LDRBi12 have same Base PointerRenato Golin2013-08-141-1/+14
* Refactor AnalyzeBranch on ARM. The previous version did not always analyzeLang Hames2013-07-191-88/+67
* Related to r181161 - Indirect branches may not be the last branch in a basicLang Hames2013-07-161-0/+7
* Fix ARM paired GPR COPY loweringJF Bastien2013-07-121-0/+3
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-161-10/+0
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-2/+1
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-2/+1
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-051-0/+2
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-2/+0
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-041-0/+2
* ARM AnalyzeBranch should conservatively return true when it sees a predicatedEvan Cheng2013-05-051-3/+9
* ARM: Use ldrd/strd to spill 64-bit pairs when available.Tim Northover2013-04-211-17/+38
* ARM: don't add FrameIndex offset for LDMIA (has no immediate)Tim Northover2013-04-201-1/+1
* ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer2013-04-051-0/+12
* Enabling the generation of dependency breakers for partial updates on Cortex-...Silviu Baranga2013-03-271-7/+5
* Adding an A15 specific optimization pass for interactions between S/D/Q regis...Silviu Baranga2013-03-151-1/+1
* Radar numbers don't belong in source code.Evan Cheng2013-02-211-2/+0
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-3/+3
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-301-2/+3
* MachineInstrBuilderize ARM.Jakob Stoklund Olesen2012-12-201-3/+4
* Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen2012-12-191-3/+4
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...Bill Wendling2012-12-191-1/+1
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+4
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-5/+5
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-0/+6
* Add GPRPair Register class to ARM.Jakob Stoklund Olesen2012-10-261-0/+19
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-12/+0
* whitespaceAndrew Trick2012-10-101-3/+3
* Create enums for the different attributes.Bill Wendling2012-10-091-1/+2
* Add LLVM support for Swift.Bob Wilson2012-09-291-9/+458
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
* More domain conversion; convert VFP VMOVS to NEON instructions in more cases ...James Molloy2012-09-181-13/+56
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-141-0/+31
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-131-13/+13
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-051-56/+31
* Strip old MachineInstrs *after* we know we can put them back.Tim Northover2012-09-051-6/+6
* Limit domain conversion to cases where it won't break dep chains.Tim Northover2012-09-011-12/+48
* Add support for moving pure S-register to NEON pipeline if desiredTim Northover2012-08-301-2/+71
* Refactor setExecutionDomain to be clearer about what it's doing and more robust.Tim Northover2012-08-291-45/+53
* Cleanup sloppy code. Jakob's review.Andrew Trick2012-08-291-4/+3
* Fix ARM vector copies of overlapping register tuples.Andrew Trick2012-08-291-0/+13
* cleanupAndrew Trick2012-08-291-21/+19
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ...Jakob Stoklund Olesen2012-08-281-10/+10
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-271-10/+10