| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI... | David Blaikie | 2013-06-16 | 1 | -6/+0 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -1/+1 |
| * | ARM: Use ldrd/strd to spill 64-bit pairs when available. | Tim Northover | 2013-04-21 | 1 | -0/+4 |
| * | ARM scheduler model: Swift has varying latencies, uops for simple ALU ops | Arnold Schwaighofer | 2013-04-05 | 1 | -0/+4 |
| * | Sort includes for all of the .h files under the 'lib' tree. These were | Chandler Carruth | 2012-12-04 | 1 | -2/+2 |
| * | misched: Use the TargetSchedModel interface wherever possible. | Andrew Trick | 2012-10-10 | 1 | -4/+0 |
| * | Add LLVM support for Swift. | Bob Wilson | 2012-09-29 | 1 | -0/+7 |
| * | Whitespace. | Bob Wilson | 2012-09-29 | 1 | -1/+1 |
| * | Implement getNumLDMAddresses and expose through ARMBaseInstrInfo. | Andrew Trick | 2012-09-14 | 1 | -0/+3 |
| * | Handle ARM MOVCC optimization in PeepholeOptimizer. | Jakob Stoklund Olesen | 2012-08-16 | 1 | -0/+7 |
| * | Fold predicable instructions into MOVCC / t2MOVCC. | Jakob Stoklund Olesen | 2012-08-15 | 1 | -0/+5 |
| * | Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle Compare | Manman Ren | 2012-06-29 | 1 | -10/+14 |
| * | misched: API for minimum vs. expected latency. | Andrew Trick | 2012-06-05 | 1 | -2/+3 |
| * | Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr. | Jakob Stoklund Olesen | 2012-04-04 | 1 | -0/+2 |
| * | ARM implement TargetInstrInfo::getNoopForMachoTarget() | Jim Grosbach | 2012-02-28 | 1 | -0/+3 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Model ARM predicated write as read-mod-write. e.g. | Evan Cheng | 2011-12-14 | 1 | -0/+4 |
| * | - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function | Evan Cheng | 2011-12-14 | 1 | -4/+3 |
| * | Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo(). | Jakob Stoklund Olesen | 2011-10-11 | 1 | -0/+2 |
| * | Implement TII::get/setExecutionDomain() for ARM. | Jakob Stoklund Olesen | 2011-09-27 | 1 | -0/+6 |
| * | Lower ARM adds/subs to add/sub after adding optional CPSR operand. | Andrew Trick | 2011-09-21 | 1 | -0/+9 |
| * | Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM. | Jakob Stoklund Olesen | 2011-08-08 | 1 | -0/+4 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -140/+0 |
| * | Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ... | Owen Anderson | 2011-07-13 | 1 | -13/+5 |
| * | Use BranchProbability instead of floating points in IfConverter. | Jakub Staszak | 2011-07-10 | 1 | -4/+4 |
| * | Hide the call to InitMCInstrInfo into tblgen generated ctor. | Evan Cheng | 2011-07-01 | 1 | -1/+4 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -6/+6 |
| * | Clean up a few 80 column violations. | Jim Grosbach | 2011-06-13 | 1 | -2/+2 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -1/+1 |
| * | Fix a typo. | Cameron Zwarich | 2011-04-13 | 1 | -3/+3 |
| * | Apply again changes to support ARM memory asm parsing. I removed | Bruno Cardoso Lopes | 2011-03-31 | 1 | -22/+2 |
| * | Revert r128632 again, until I figure out what break the tests | Bruno Cardoso Lopes | 2011-03-31 | 1 | -2/+22 |
| * | Reapply r128585 without generating a lib depedency cycle. An updated log: | Bruno Cardoso Lopes | 2011-03-31 | 1 | -22/+2 |
| * | Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" | Matt Beaumont-Gay | 2011-03-31 | 1 | -1/+19 |
| * | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and | Bruno Cardoso Lopes | 2011-03-30 | 1 | -19/+1 |
| * | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov | 2011-03-05 | 1 | -4/+4 |
| * | VFP single precision arith instructions can go down to NEON pipeline, but on ... | Evan Cheng | 2011-02-22 | 1 | -1/+2 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -1/+2 |
| * | Various bits of framework needed for precise machine-level selection | Andrew Trick | 2010-12-24 | 1 | -1/+6 |
| * | Making use of VFP / NEON floating point multiply-accumulate / subtraction is | Evan Cheng | 2010-12-05 | 1 | -1/+39 |
| * | s/ARM::BRIND/ARM::BX/g to coincide with r120366. | Bill Wendling | 2010-11-30 | 1 | -1/+1 |
| * | Move callee-saved regs spills / reloads to TFI | Anton Korobeynikov | 2010-11-27 | 1 | -19/+0 |
| * | Rewrite stack callee saved spills and restores to use push/pop instructions. | Eric Christopher | 2010-11-18 | 1 | -0/+15 |
| * | Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, | Evan Cheng | 2010-11-17 | 1 | -0/+5 |
| * | Code clean up. The peephole pass should be the one updating the instruction | Evan Cheng | 2010-11-15 | 1 | -2/+1 |
| * | Revert this temporarily. | Eric Christopher | 2010-11-11 | 1 | -5/+0 |
| * | Change the prologue and epilogue to use push/pop for the low ARM registers. | Eric Christopher | 2010-11-11 | 1 | -0/+5 |
| * | Two sets of changes. Sorry they are intermingled. | Evan Cheng | 2010-11-03 | 1 | -7/+15 |
| * | First part of refactoring ARM addrmode2 (load/store) instructions to be more | Jim Grosbach | 2010-10-26 | 1 | -0/+1 |
| * | Use instruction itinerary to determine what instructions are 'cheap'. | Evan Cheng | 2010-10-26 | 1 | -0/+2 |
