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* * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same asBill Wendling2010-11-301-0/+4
| | | | | | | | | | | t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-301-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
* Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almostBill Wendling2010-11-301-2/+4
| | | | | | | | | | | certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename BX/BRIND/etc patterns to clarify which is actually the BX instructionJim Grosbach2010-11-301-4/+4
| | | | | | and which are pseudos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct Thumb2 encodings for a much wider range of loads and stores.Owen Anderson2010-11-301-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-301-0/+2
| | | | | | | | The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide Thumb2 encodings for basic loads and stores.Owen Anderson2010-11-291-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the sameBill Wendling2010-11-201-9/+21
| | | | | | | value that the one in ARMMCCodeEmitter.cpp does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanups to a few llvm_unreachable() calls.Jim Grosbach2010-11-191-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim2010-11-181-0/+5
| | | | | | | | | | | .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't markJim Grosbach2010-11-171-0/+8
| | | | | | it as such. Add some encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment typo.Jim Grosbach2010-11-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119573 91177308-0d34-0410-b5e6-96231b3b80d8
* The machine instruction no longer encodes the submode as a separate operand. WeBill Wendling2010-11-171-4/+4
| | | | | | | should get the submode from the load/store multiple instruction's opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.Jim Grosbach2010-11-151-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-121-5/+5
| | | | | | movi+orr or movw+movt depending on the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
* First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson2010-11-121-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-111-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-111-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-111-0/+2
| | | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-111-0/+2
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-111-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM STRH encoding information.Jim Grosbach2010-11-111-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-101-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-091-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-11/+30
| | | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-021-19/+20
| | | | | | | | | with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename encoder methods to match naming convention.Owen Anderson2010-11-021-5/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct NEON encodings for vld2, vld3, and vld4 basic variants.Owen Anderson2010-11-021-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson2010-11-021-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-301-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-291-1/+1
| | | | | | encoder functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-2/+3
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-271-0/+2
| | | | | | | | | encoding for specifying fractional bits for fixed point conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
* JIT imm12 encoding for constant pool entry references.Jim Grosbach2010-10-271-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM JIT fix for LDRi12 and company.Jim Grosbach2010-10-271-4/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
* The new LDR* instruction patterns should handle the necessary encoding ofJim Grosbach2010-10-271-0/+7
| | | | | | | operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+2
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
* fix memory-layout assumption which only holds on little-endian systemsGabor Greif2010-10-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Binary encoding information for BFC/BFI instructions.Jim Grosbach2010-10-211-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encodings for movement between ARM core registers and single-precisionBill Wendling2010-10-201-1/+1
| | | | | | | registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMCodeEmitter::emitMiscInstruction is dead. Long liveBill Wendling2010-10-151-45/+1
| | | | | | | ARMCodeEmitter::emitMiscInstruction! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-151-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'Jim Grosbach2010-10-141-2/+2
| | | | | | pseudonym. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoding for 'fmstat'.Bill Wendling2010-10-141-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add encodings for multiply add/subtract instructions in all their glory.Bill Wendling2010-10-141-9/+1
| | | | | | | | - Add missing patterns for some multiply add/subtract instructions. - Add encodings for VMRS and VMSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-131-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the rest of the ARM so_reg encoding options (register shifted register)Jim Grosbach2010-10-121-0/+2
| | | | | | | and move to a custom operand encoder. Remove the last of the special handling stuff from ARMMCCodeEmitter::EncodeInstruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the ARM so_imm encoding into a custom operand encoder and remove theJim Grosbach2010-10-121-0/+2
| | | | | | | explicit handling of the instructions referencing it from the MC code emitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
* Add custom encoder for the 's' bit denoting whether an ARM arithmeticJim Grosbach2010-10-121-0/+11
| | | | | | | instruction should set the processor status flags or not. Remove the now unnecessary special handling for the bit from the MCCodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
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