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path: root/lib/Target/ARM/ARMISelLowering.cpp
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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-281/+176
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-308/+403
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-143/+493
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-28/+177
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-297/+591
* Update to LLVM 3.5a.Stephen Hines2014-04-241-926/+177
* ARM: produce friendly error for invalid inline asmTim Northover2013-11-141-0/+4
* Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.Bob Wilson2013-11-031-0/+77
* Legalize: Improve legalization of long vector extends.Jim Grosbach2013-10-311-55/+0
* Struct byval cleanup: add helper functions to reduce code duplication.Manman Ren2013-10-291-180/+117
* ARM: don't expand atomicrmw inline on Cortex-M0Tim Northover2013-10-251-9/+10
* ARM: Tweak usage of '*vfp' compiler_rt functions.Jim Grosbach2013-10-241-1/+2
* Remove class abstraction from ARM struct byval loweringDavid Peixotto2013-10-241-553/+262
* ARM: Use non-VFP softcalls on embedded Darwinish targetsTim Northover2013-10-241-1/+1
* 17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targetsDavid Peixotto2013-10-171-7/+108
* Refactor lowering for COPY_STRUCT_BYVAL_I32David Peixotto2013-10-171-170/+460
* Struct byval: fix a copy-paste error for thumb2.Manman Ren2013-10-151-1/+1
* Struct byval: use the correct alignment for loads generated to loadManman Ren2013-10-071-1/+2
* ARM: do not add a regmask for TAILJUMPsMatthias Braun2013-10-041-16/+18
* ARM: support interrupt attributeTim Northover2013-10-011-1/+55
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-122/+161
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-251-0/+10
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-131-2/+2
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-2/+2
* Clean up some usage of Triple. The base class has methods for determining if...Cameron Esfahani2013-08-291-1/+1
* ARM: Use "dmb sy" for barriers on M-class CPUsTim Northover2013-08-281-1/+4
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-231-0/+16
* [ARMv8] Add CodeGen support for VSEL.Joey Gouly2013-08-221-1/+93
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-221-0/+4
* ARM: implement some simple f64 materializations.Tim Northover2013-08-201-10/+40
* ARM: implement allowTruncateForTailCallTim Northover2013-08-061-0/+15
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-14/+21
* [ARM][ISel] Improve the lowering of vector loads.Quentin Colombet2013-07-231-1/+3
* ARM: allow printing of ARM atomic DAG nodes.Tim Northover2013-07-161-0/+13
* ARM: implement ldrex, strex and clrex intrinsicsTim Northover2013-07-161-0/+24
* ARM EABI divmod supportRenato Golin2013-07-161-2/+78
* Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]).Craig Topper2013-07-151-1/+1
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...Craig Topper2013-07-141-5/+5
* ARM: Improve codegen for generic vselect.Jim Grosbach2013-07-081-0/+18
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-2/+0
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+2
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-2/+0
* [ARM] Improve the instruction selection of vector loads.Quentin Colombet2013-07-031-0/+94
* ARM: relax the atomic release barrier to "dmb ishst" on SwiftTim Northover2013-07-031-1/+11
* Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")Tim Northover2013-07-011-5/+1
* ARM: relax the atomic release barrier to "dmb ishst"Tim Northover2013-07-011-1/+5
* ARM: ensure fixed-point conversions have sane typesTim Northover2013-06-281-5/+36
* ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is n...Stephen Lin2013-06-261-3/+10
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-221-1/+1
* [ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implyin...Michael Gottesman2013-06-181-1/+11
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