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path: root/lib/Target/ARM/ARMISelLowering.cpp
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* Add support for NEON VMVN immediate instructions.Bob Wilson2010-07-141-3/+18
* Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.Bob Wilson2010-07-141-0/+29
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-131-118/+26
* Extend the r107852 optimization which turns some fp compare to code sequence ...Evan Cheng2010-07-131-68/+208
* Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson2010-07-131-19/+16
* Remove some code that doesn't appear to do anything. All the ARM callBob Wilson2010-07-121-5/+0
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-0/+4
* Check for FiniteOnlyFPMath as well.Evan Cheng2010-07-081-1/+1
* r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.Evan Cheng2010-07-081-3/+5
* Optimize some vfp comparisons to integer ones. This patch implements the simp...Evan Cheng2010-07-081-10/+45
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-081-7/+14
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-071-4/+7
* Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's whereJim Grosbach2010-07-071-2/+4
* By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing ratherJim Grosbach2010-07-061-0/+2
* Propagate debug loc.Devang Patel2010-07-061-2/+2
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-21/+31
* Revert r107655.Dan Gohman2010-07-061-31/+21
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-21/+31
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill sl...Evan Cheng2010-07-031-8/+5
* ARM function alignments were off by a power of two. svn 83242 changedBob Wilson2010-07-011-1/+1
* Remove initialized but otherwise unused variables.Duncan Sands2010-06-291-1/+0
* Followup to r106770: actually generate SXTB and SXTH for sign-extensions.Eli Friedman2010-06-261-5/+2
* It's now possible to run code placement pass for ARM.Evan Cheng2010-06-261-4/+8
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-251-17/+0
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-251-3/+1
* Reduce indentation.Bob Wilson2010-06-251-8/+7
* Do not do tail calls to external symbols. If theDale Johannesen2010-06-231-12/+9
* When using libcall expansions for the atomic intrinsics, the explicitJim Grosbach2010-06-231-0/+2
* sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.Bob Wilson2010-06-211-1/+1
* Fix error message to match function name.Bob Wilson2010-06-191-1/+1
* Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emi...Evan Cheng2010-06-191-8/+17
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-181-0/+4
* Enable Expand handling of atomics for subtargets that can't do them inline.Jim Grosbach2010-06-181-3/+39
* Enable tail calls on ARM by default, with someDale Johannesen2010-06-181-1/+1
* Last round of changes for ARM tail calls.Dale Johannesen2010-06-181-7/+14
* Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86Jakob Stoklund Olesen2010-06-181-1/+1
* Thumb1 and any pre-v6 ARM target should use the libcall expansion ofJim Grosbach2010-06-171-1/+6
* simplify code a bit and add a more explanatory assert for cases thatJim Grosbach2010-06-171-15/+11
* format and 80-column cleanupJim Grosbach2010-06-161-5/+4
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-4/+1
* Make post-ra scheduling, anti-dep breaking, and register scavenger (conservat...Evan Cheng2010-06-161-1/+6
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-5/+8
* Add basic support for NEON modified immediates besides VMOV.Bob Wilson2010-06-151-4/+15
* Rename functions referring to VMOV immediates to refer to NEON "modifiedBob Wilson2010-06-141-17/+21
* Add a missing bitcast. This code used to only handle conversions betweenBob Wilson2010-06-111-1/+2
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-26/+89
* Further changes for Neon vector shuffles:Bob Wilson2010-06-071-52/+56
* Improvements to tail call code. No functional effectDale Johannesen2010-06-051-20/+22
* More thoroughly disable tails calls by default.Dale Johannesen2010-06-041-3/+3
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-041-19/+16
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