| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Track IR ordering of SelectionDAG nodes 2/4. | Andrew Trick | 2013-05-25 | 1 | -10/+10 |
| * | PR15868 fix. | Stepan Dyatkovskiy | 2013-05-20 | 1 | -0/+2 |
| * | Add LLVMContext argument to getSetCCResultType | Matt Arsenault | 2013-05-18 | 1 | -1/+1 |
| * | For ARM backend, fixed "byval" attribute support. | Stepan Dyatkovskiy | 2013-05-05 | 1 | -0/+2 |
| * | Refactoring patch. | Stepan Dyatkovskiy | 2013-04-30 | 1 | -5/+10 |
| * | Add CodeGen support for functions that always return arguments via a new para... | Stephen Lin | 2013-04-20 | 1 | -1/+2 |
| * | Switch TargetTransformInfo from an immutable analysis pass that requires | Chandler Carruth | 2013-01-07 | 1 | -11/+0 |
| * | Revert "Adding support for llvm.arm.neon.vaddl[su].* and" | Bob Wilson | 2012-12-20 | 1 | -8/+0 |
| * | Adding support for llvm.arm.neon.vaddl[su].* and | Renato Golin | 2012-12-20 | 1 | -0/+8 |
| * | Change TargetLowering::findRepresentativeClass to take an MVT, instead | Patrik Hagglund | 2012-12-19 | 1 | -1/+1 |
| * | Change TargetLowering::getRegClassFor to take an MVT, instead of EVT. | Patrik Hagglund | 2012-12-13 | 1 | -1/+1 |
| * | Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I | Evan Cheng | 2012-12-12 | 1 | -1/+1 |
| * | - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term. | Evan Cheng | 2012-12-12 | 1 | -8/+1 |
| * | Avoid using lossy load / stores for memcpy / memset expansion. e.g. | Evan Cheng | 2012-12-12 | 1 | -0/+7 |
| * | Replace TargetLowering::isIntImmLegal() with | Evan Cheng | 2012-12-11 | 1 | -2/+11 |
| * | Revert EVT->MVT changes, r169836-169851, due to buildbot failures. | Patrik Hagglund | 2012-12-11 | 1 | -2/+2 |
| * | Change TargetLowering::findRepresentativeClass to take an MVT, instead | Patrik Hagglund | 2012-12-11 | 1 | -1/+1 |
| * | Change TargetLowering::getRegClassFor to take an MVT, instead of EVT. | Patrik Hagglund | 2012-12-11 | 1 | -1/+1 |
| * | Some enhancements for memcpy / memset inline expansion. | Evan Cheng | 2012-12-10 | 1 | -2/+5 |
| * | Add a 'using' declaration to suppress GCC's -Woverloaded-virtual while we | Matt Beaumont-Gay | 2012-12-06 | 1 | -0/+1 |
| * | Replace r169459 with something safer. Rather than having computeMaskedBits to | Evan Cheng | 2012-12-06 | 1 | -5/+2 |
| * | Let targets provide hooks that compute known zero and ones for any_extend | Evan Cheng | 2012-12-06 | 1 | -0/+5 |
| * | Sort includes for all of the .h files under the 'lib' tree. These were | Chandler Carruth | 2012-12-04 | 1 | -3/+3 |
| * | Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend. | Silviu Baranga | 2012-11-29 | 1 | -2/+8 |
| * | ARM: Implement CanLowerReturn so large vectors get expanded into sret. | Benjamin Kramer | 2012-11-28 | 1 | -0/+6 |
| * | Use empty parens for empty function parameter list instead of '(void)'. | Dmitri Gribenko | 2012-11-15 | 1 | -1/+1 |
| * | ARM: | Stepan Dyatkovskiy | 2012-10-19 | 1 | -1/+2 |
| * | Issue: | Stepan Dyatkovskiy | 2012-10-16 | 1 | -1/+1 |
| * | Issue description: | Stepan Dyatkovskiy | 2012-10-10 | 1 | -1/+4 |
| * | Patch to implement UMLAL/SMLAL instructions for the ARM architecture | Arnold Schwaighofer | 2012-09-04 | 1 | -0/+3 |
| * | Not all targets have efficient ISel code generation for select instructions. | Nadav Rotem | 2012-09-02 | 1 | -0/+5 |
| * | Remove the CAND/COR/CXOR custom ISD nodes and their select code. | Jakob Stoklund Olesen | 2012-08-18 | 1 | -3/+0 |
| * | Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM | Arnold Schwaighofer | 2012-08-12 | 1 | -3/+0 |
| * | Change addTypeForNeon to use MVT instead of EVT so all the calls to getSimple... | Craig Topper | 2012-08-12 | 1 | -3/+3 |
| * | Patch to implement UMLAL/SMLAL instructions for the ARM architecture | Arnold Schwaighofer | 2012-08-09 | 1 | -0/+3 |
| * | Fall back to selection DAG isel for calls to builtin functions. | Bob Wilson | 2012-08-03 | 1 | -2/+4 |
| * | Re-enable the CMN instruction. | Bill Wendling | 2012-06-11 | 1 | -0/+1 |
| * | ARM: properly handle alignment for struct byval. | Manman Ren | 2012-06-01 | 1 | -0/+3 |
| * | ARM: support struct byval in llvm | Manman Ren | 2012-06-01 | 1 | -0/+3 |
| * | Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall | Justin Holewinski | 2012-05-25 | 1 | -7/+1 |
| * | Make ARM and Mips use TargetMachine::getTLSModel() | Hans Wennborg | 2012-05-04 | 1 | -1/+2 |
| * | Fix a long standing tail call optimization bug. When a libcall is emitted | Evan Cheng | 2012-04-10 | 1 | -1/+1 |
| * | Always compute all the bits in ComputeMaskedBits. | Rafael Espindola | 2012-04-04 | 1 | -1/+0 |
| * | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 2012-03-17 | 1 | -0/+1 |
| * | Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on | Lang Hames | 2012-03-15 | 1 | -0/+2 |
| * | Re-commit r151623 with fix. Only issue special no-return calls if it's a dire... | Evan Cheng | 2012-02-28 | 1 | -1/+1 |
| * | Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre... | Daniel Dunbar | 2012-02-28 | 1 | -1/+1 |
| * | Some ARM implementaions, e.g. A-series, does return stack prediction. That is, | Evan Cheng | 2012-02-28 | 1 | -1/+1 |
| * | Optimize a couple of common patterns involving conditional moves where the false | Evan Cheng | 2012-02-23 | 1 | -0/+4 |
| * | Make all pointers to TargetRegisterClass const since they are all pointers to... | Craig Topper | 2012-02-22 | 1 | -1/+1 |
