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path: root/lib/Target/ARM/ARMISelLowering.h
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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-18/+15
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-10/+9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-7/+29
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-0/+6
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-5/+23
* Update to LLVM 3.5a.Stephen Hines2014-04-241-106/+83
* Merging r196269:Bill Wendling2013-12-071-0/+6
* Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.Bob Wilson2013-11-031-0/+1
* ARM: support interrupt attributeTim Northover2013-10-011-0/+1
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-15/+3
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-1/+0
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-231-0/+2
* ARM: implement allowTruncateForTailCallTim Northover2013-08-061-0/+3
* ARM EABI divmod supportRenato Golin2013-07-161-0/+1
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...Craig Topper2013-07-141-1/+1
* Fix typoStephen Lin2013-07-101-1/+1
* Explicitly define ARMISelLowering::isFMAFasterThanFMulAndFAdd. No functionali...Stephen Lin2013-07-101-0/+11
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-221-1/+1
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-10/+10
* PR15868 fix.Stepan Dyatkovskiy2013-05-201-0/+2
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-1/+1
* For ARM backend, fixed "byval" attribute support.Stepan Dyatkovskiy2013-05-051-0/+2
* Refactoring patch.Stepan Dyatkovskiy2013-04-301-5/+10
* Add CodeGen support for functions that always return arguments via a new para...Stephen Lin2013-04-201-1/+2
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-071-11/+0
* Revert "Adding support for llvm.arm.neon.vaddl[su].* and"Bob Wilson2012-12-201-8/+0
* Adding support for llvm.arm.neon.vaddl[su].* andRenato Golin2012-12-201-0/+8
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-191-1/+1
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-131-1/+1
* Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng2012-12-121-1/+1
* - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng2012-12-121-8/+1
* Avoid using lossy load / stores for memcpy / memset expansion. e.g.Evan Cheng2012-12-121-0/+7
* Replace TargetLowering::isIntImmLegal() withEvan Cheng2012-12-111-2/+11
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-2/+2
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-111-1/+1
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-111-1/+1
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-101-2/+5
* Add a 'using' declaration to suppress GCC's -Woverloaded-virtual while weMatt Beaumont-Gay2012-12-061-0/+1
* Replace r169459 with something safer. Rather than having computeMaskedBits toEvan Cheng2012-12-061-5/+2
* Let targets provide hooks that compute known zero and ones for any_extendEvan Cheng2012-12-061-0/+5
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-3/+3
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-291-2/+8
* ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer2012-11-281-0/+6
* Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko2012-11-151-1/+1
* ARM:Stepan Dyatkovskiy2012-10-191-1/+2
* Issue:Stepan Dyatkovskiy2012-10-161-1/+1
* Issue description:Stepan Dyatkovskiy2012-10-101-1/+4
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-041-0/+3
* Not all targets have efficient ISel code generation for select instructions.Nadav Rotem2012-09-021-0/+5
* Remove the CAND/COR/CXOR custom ISD nodes and their select code.Jakob Stoklund Olesen2012-08-181-3/+0