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path: root/lib/Target/ARM/ARMInstrInfo.cpp
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* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
* ARM: Fix ELF global base reg intialization.Jim Grosbach2013-08-261-3/+8
* When initializing the PIC global base register on ARM/ELF add pc to fix the a...Benjamin Kramer2013-08-161-0/+4
* Create a constant pool symbol for the GOT in the ARMCGBR the same way weChandler Carruth2013-07-271-7/+8
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-271-0/+62
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-181-1/+2
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-0/+17
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w...Owen Anderson2011-08-261-2/+4
* Split am2offset into register addend and immediate addend forms, necessary fo...Owen Anderson2011-07-261-6/+12
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A...Evan Cheng2011-07-201-1/+1
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+0
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+o...Evan Cheng2010-11-121-24/+0
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-291-2/+1
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-2/+2
* Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach2010-10-271-1/+1
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-1/+1
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-1/+1
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-19/+0
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-3/+3
* Refactor code.Evan Cheng2009-11-081-11/+8
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-5/+12
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls,...Anton Korobeynikov2009-11-021-1/+1
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-281-0/+1
* Trim more includes.Evan Cheng2009-10-221-1/+0
* Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudoEvan Cheng2009-09-281-1/+0
* Fix thinko in my recent movt commit: it's not safe to remat movt, since it ha...Anton Korobeynikov2009-09-281-2/+0
* Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.Anton Korobeynikov2009-09-271-0/+3
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-1/+1
* Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster...Evan Cheng2009-08-041-160/+0
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-5/+164
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-13/+0
* More DCE.Evan Cheng2009-07-271-4/+0
* Get rid of more dead code.Evan Cheng2009-07-271-2/+0
* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-3/+0
* Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate m...Evan Cheng2009-07-271-2/+0
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-3/+0
* FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructi...Evan Cheng2009-07-241-8/+0
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index eliminatio...David Goodwin2009-07-241-7/+4
* Fix frame index elimination to correctly handle thumb-2 addressing modes that...David Goodwin2009-07-231-0/+5
* Let callers decide the sub-register index on the def operand of rematerialize...Evan Cheng2009-07-161-2/+2
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-1/+2
* Checkpoint Thumb2 Instr info work. Generalized base code so that it can be sh...David Goodwin2009-07-081-827/+48
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1Ins...David Goodwin2009-07-021-293/+306
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the...Evan Cheng2009-07-011-8/+26
* Improve Thumb-2 jump table support.David Goodwin2009-06-301-5/+9
* Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.David Goodwin2009-06-301-17/+30