| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -3/+3 |
| * | ARM: Use the PICADD opcode calculated. | Jim Grosbach | 2013-09-10 | 1 | -2/+6 |
| * | ARM: Fix ELF global base reg intialization. | Jim Grosbach | 2013-08-26 | 1 | -3/+8 |
| * | When initializing the PIC global base register on ARM/ELF add pc to fix the a... | Benjamin Kramer | 2013-08-16 | 1 | -0/+4 |
| * | Create a constant pool symbol for the GOT in the ARMCGBR the same way we | Chandler Carruth | 2013-07-27 | 1 | -7/+8 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -1/+1 |
| * | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 2013-01-02 | 1 | -2/+2 |
| * | Move TargetData to DataLayout. | Micah Villmow | 2012-10-08 | 1 | -1/+1 |
| * | [arm-fast-isel] Add support for ELF PIC. | Jush Lu | 2012-09-27 | 1 | -0/+62 |
| * | ARM: Define generic HINT instruction. | Jim Grosbach | 2012-06-18 | 1 | -1/+2 |
| * | ARM implement TargetInstrInfo::getNoopForMachoTarget() | Jim Grosbach | 2012-02-28 | 1 | -0/+17 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson | 2011-08-26 | 1 | -2/+4 |
| * | Split am2offset into register addend and immediate addend forms, necessary fo... | Owen Anderson | 2011-07-26 | 1 | -6/+12 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc | Evan Cheng | 2011-06-28 | 1 | -1/+0 |
| * | Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+o... | Evan Cheng | 2010-11-12 | 1 | -24/+0 |
| * | Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in | Jim Grosbach | 2010-10-29 | 1 | -2/+1 |
| * | Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like | Jim Grosbach | 2010-10-27 | 1 | -2/+2 |
| * | Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on | Jim Grosbach | 2010-10-27 | 1 | -1/+1 |
| * | First part of refactoring ARM addrmode2 (load/store) instructions to be more | Jim Grosbach | 2010-10-26 | 1 | -1/+1 |
| * | Slightly change the meaning of the reMaterialize target hook when the original | Jakob Stoklund Olesen | 2010-06-02 | 1 | -1/+1 |
| * | Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of | Dan Gohman | 2009-12-05 | 1 | -19/+0 |
| * | - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. | Evan Cheng | 2009-11-14 | 1 | -3/+3 |
| * | Refactor code. | Evan Cheng | 2009-11-08 | 1 | -11/+8 |
| * | - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative | Evan Cheng | 2009-11-06 | 1 | -5/+12 |
| * | Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls,... | Anton Korobeynikov | 2009-11-02 | 1 | -1/+1 |
| * | Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the | Bob Wilson | 2009-10-28 | 1 | -0/+1 |
| * | Trim more includes. | Evan Cheng | 2009-10-22 | 1 | -1/+0 |
| * | Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo | Evan Cheng | 2009-09-28 | 1 | -1/+0 |
| * | Fix thinko in my recent movt commit: it's not safe to remat movt, since it ha... | Anton Korobeynikov | 2009-09-28 | 1 | -2/+0 |
| * | Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. | Anton Korobeynikov | 2009-09-27 | 1 | -0/+3 |
| * | Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. | Chris Lattner | 2009-08-22 | 1 | -1/+1 |
| * | Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster... | Evan Cheng | 2009-08-04 | 1 | -160/+0 |
| * | Move the getInlineAsmLength virtual method from TAI to TII, where | Chris Lattner | 2009-08-02 | 1 | -5/+164 |
| * | - More refactoring. This gets rid of all of the getOpcode calls. | Evan Cheng | 2009-07-28 | 1 | -13/+0 |
| * | More DCE. | Evan Cheng | 2009-07-27 | 1 | -4/+0 |
| * | Get rid of more dead code. | Evan Cheng | 2009-07-27 | 1 | -2/+0 |
| * | Get rid of some more getOpcode calls. | Evan Cheng | 2009-07-27 | 1 | -3/+0 |
| * | Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate m... | Evan Cheng | 2009-07-27 | 1 | -2/+0 |
| * | Change Thumb2 jumptable codegen to one that uses two level jumps: | Evan Cheng | 2009-07-25 | 1 | -3/+0 |
| * | FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructi... | Evan Cheng | 2009-07-24 | 1 | -8/+0 |
| * | Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index eliminatio... | David Goodwin | 2009-07-24 | 1 | -7/+4 |
| * | Fix frame index elimination to correctly handle thumb-2 addressing modes that... | David Goodwin | 2009-07-23 | 1 | -0/+5 |
| * | Let callers decide the sub-register index on the def operand of rematerialize... | Evan Cheng | 2009-07-16 | 1 | -2/+2 |
| * | Generalize opcode selection in ARMBaseRegisterInfo. | David Goodwin | 2009-07-08 | 1 | -1/+2 |
| * | Checkpoint Thumb2 Instr info work. Generalized base code so that it can be sh... | David Goodwin | 2009-07-08 | 1 | -827/+48 |
| * | Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1Ins... | David Goodwin | 2009-07-02 | 1 | -293/+306 |
| * | Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the... | Evan Cheng | 2009-07-01 | 1 | -8/+26 |
| * | Improve Thumb-2 jump table support. | David Goodwin | 2009-06-30 | 1 | -5/+9 |
