| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add support to the ARM asm parser for the register-shifted-register forms of ... | Owen Anderson | 2011-03-18 | 1 | -2/+8 |
| * | Match a few more obvious patterns to revsh. rdar://9147637. | Evan Cheng | 2011-03-18 | 1 | -1/+9 |
| * | Clean whitespace. | Owen Anderson | 2011-03-18 | 1 | -8/+8 |
| * | Add "swi" which is an obsolete mnemonic for "svc". | Nick Lewycky | 2011-03-17 | 1 | -0/+1 |
| * | Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches. | Jim Grosbach | 2011-03-15 | 1 | -27/+22 |
| * | Add FIXME. | Jim Grosbach | 2011-03-12 | 1 | -0/+3 |
| * | Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same | Jim Grosbach | 2011-03-12 | 1 | -27/+13 |
| * | Add a FIXME. | Jim Grosbach | 2011-03-11 | 1 | -0/+2 |
| * | Pseudo-ize the ARM 'B' instruction. | Jim Grosbach | 2011-03-11 | 1 | -7/+3 |
| * | Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- | Jim Grosbach | 2011-03-11 | 1 | -10/+4 |
| * | This FIXME has been fixed. | Jim Grosbach | 2011-03-11 | 1 | -3/+0 |
| * | Properly pseudo-ize ARM MVNCCi. | Jim Grosbach | 2011-03-11 | 1 | -12/+4 |
| * | Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4). | Jim Grosbach | 2011-03-11 | 1 | -3/+3 |
| * | Properly pseudo-ize ARM MOVCCi and MOVCCi16. | Jim Grosbach | 2011-03-11 | 1 | -26/+9 |
| * | Properly pseudo-ize MOVCCr and MOVCCs. | Jim Grosbach | 2011-03-10 | 1 | -26/+9 |
| * | DMB can just be a pat referencing MCR. | Jim Grosbach | 2011-03-10 | 1 | -7/+6 |
| * | Reorganize a bit. No functional change, just moving patterns up. | Jim Grosbach | 2011-03-10 | 1 | -232/+233 |
| * | Remove unused conditional negate operations. | Bob Wilson | 2011-03-05 | 1 | -2/+0 |
| * | pr9367: Add missing predicated BLX instructions. | Bob Wilson | 2011-03-03 | 1 | -1/+19 |
| * | Fixes an assertion failure while disassembling ARM rsbs reg/reg form. | Kevin Enderby | 2011-03-02 | 1 | -0/+13 |
| * | Add patterns to use post-increment addressing for Neon VST1-lane instructions. | Bob Wilson | 2011-02-25 | 1 | -1/+3 |
| * | Add assembly parsing support for "msr" and also fix its encoding. Also add | Bruno Cardoso Lopes | 2011-02-18 | 1 | -21/+29 |
| * | Fix encoding and add parsing support for the arm/thumb CPS instruction: | Bruno Cardoso Lopes | 2011-02-14 | 1 | -13/+29 |
| * | AsmMatcher custom operand parser failure enhancements. | Jim Grosbach | 2011-02-12 | 1 | -2/+2 |
| * | Add support for parsing dmb/dsb instructions | Bruno Cardoso Lopes | 2011-02-07 | 1 | -0/+1 |
| * | Remove the MCR asm parser hack and start using the custom target specific asm | Bruno Cardoso Lopes | 2011-02-07 | 1 | -0/+14 |
| * | Fix a comment: addrmode6 no longer includes the optional writeback flag. | Bob Wilson | 2011-02-07 | 1 | -1/+1 |
| * | Remove inaccurate comments: so_imm and t2_so_imm operands are not encoded | Bob Wilson | 2011-02-07 | 1 | -4/+1 |
| * | Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. | Jason W Kim | 2011-02-04 | 1 | -3/+19 |
| * | Fix PLD encoding. | Evan Cheng | 2011-01-27 | 1 | -2/+2 |
| * | Last round of fixes for movw + movt global address codegen. | Evan Cheng | 2011-01-21 | 1 | -9/+15 |
| * | Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", | Bruno Cardoso Lopes | 2011-01-21 | 1 | -8/+12 |
| * | - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same... | Bruno Cardoso Lopes | 2011-01-20 | 1 | -9/+35 |
| * | Refactor mcr* and mr*c instructions into classes with the same encoding. No f... | Bruno Cardoso Lopes | 2011-01-20 | 1 | -108/+46 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -6/+17 |
| * | Fix the encoding of mrrc and mcrr family of instructions. Also add testcases ... | Bruno Cardoso Lopes | 2011-01-19 | 1 | -16/+16 |
| * | Don't forget to emit the load from indirect symbol when using movw + movt to ... | Evan Cheng | 2011-01-19 | 1 | -2/+2 |
| * | Fix MRS encoding for arm and thumb. | Bruno Cardoso Lopes | 2011-01-18 | 1 | -4/+8 |
| * | Add support for parsing and encoding ARM's official syntax for the BFI instru... | Bruno Cardoso Lopes | 2011-01-18 | 1 | -0/+31 |
| * | Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. | Evan Cheng | 2011-01-17 | 1 | -2/+17 |
| * | Provide instruction sizes for ARMv5 variants of MUL instructions. | Anton Korobeynikov | 2011-01-16 | 1 | -29/+30 |
| * | 80-col. | Eric Christopher | 2011-01-15 | 1 | -2/+4 |
| * | Add support to the ARM MC infrastructure to support mcr and friends. This req... | Owen Anderson | 2011-01-13 | 1 | -24/+136 |
| * | Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step | Evan Cheng | 2011-01-13 | 1 | -6/+6 |
| * | ARM/MC: Mark several '...S' instructions as codegen only, they aren't real | Daniel Dunbar | 2011-01-10 | 1 | -4/+6 |
| * | Fix comment typo. | Bob Wilson | 2011-01-06 | 1 | -1/+1 |
| * | Model operand restrictions of mul-like instructions on ARMv5 via | Anton Korobeynikov | 2011-01-01 | 1 | -8/+57 |
| * | Remove dead patterns. | Jim Grosbach | 2010-12-23 | 1 | -26/+0 |
| * | Flag -> Glue, the ongoing saga | Chris Lattner | 2010-12-23 | 1 | -15/+15 |
| * | Add Neon VCVT instructions for f32 <-> f16 conversions. | Bob Wilson | 2010-12-15 | 1 | -0/+1 |
