| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update ARM Insn encoding to get endian-ness to match the documentation (31-0 ... | Jim Grosbach | 2008-10-14 | 1 | -38/+38 |
| * | Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as | Chris Lattner | 2008-10-11 | 1 | -2/+2 |
| * | Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to ... | Jim Grosbach | 2008-10-07 | 1 | -1/+1 |
| * | Fix Opcode values of CMP and CMN | Jim Grosbach | 2008-10-07 | 1 | -4/+4 |
| * | Fix addrmode1 instruction encodings; fix bx_ret encoding. | Evan Cheng | 2008-09-17 | 1 | -28/+47 |
| * | Revert 56176. All those instruction formats are still needed. | Evan Cheng | 2008-09-13 | 1 | -31/+31 |
| * | Eliminate unnecessary instruction formats. | Evan Cheng | 2008-09-12 | 1 | -31/+31 |
| * | Rename ConstantSDNode::getValue to getZExtValue, for consistency | Dan Gohman | 2008-09-12 | 1 | -15/+18 |
| * | Control flow instruction encodings. | Evan Cheng | 2008-09-01 | 1 | -5/+5 |
| * | ldm / stm instruction encodings. | Evan Cheng | 2008-09-01 | 1 | -3/+3 |
| * | AXI2 and AXI3 instruction encodings. | Evan Cheng | 2008-09-01 | 1 | -10/+10 |
| * | addrmode3 instruction encodings. | Evan Cheng | 2008-09-01 | 1 | -14/+14 |
| * | Rest of addrmode2 instruction encodings. | Evan Cheng | 2008-09-01 | 1 | -10/+10 |
| * | Addr2 word / byte load encodings. | Evan Cheng | 2008-08-31 | 1 | -3/+3 |
| * | MVN is addrmode1. | Evan Cheng | 2008-08-29 | 1 | -7/+7 |
| * | Refactor ARM instruction format definitions into a separate file. No function... | Evan Cheng | 2008-08-28 | 1 | -215/+4 |
| * | Rename SDOperand to SDValue. | Dan Gohman | 2008-07-27 | 1 | -1/+1 |
| * | Replace all target specific implicit def instructions with a target independe... | Evan Cheng | 2008-03-15 | 1 | -6/+0 |
| * | Final de-tabification. | Bill Wendling | 2008-02-27 | 1 | -2/+2 |
| * | This commit changes: | Chris Lattner | 2008-01-17 | 1 | -8/+0 |
| * | rename SDTRet -> SDTNone. | Chris Lattner | 2008-01-15 | 1 | -1/+1 |
| * | get def use info more correct. | Chris Lattner | 2008-01-10 | 1 | -1/+4 |
| * | Only mark instructions that load a single value without extension as isSimple... | Evan Cheng | 2008-01-07 | 1 | -6/+5 |
| * | rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. | Chris Lattner | 2008-01-06 | 1 | -5/+5 |
| * | rename isStore -> mayStore to more accurately reflect what it captures. | Chris Lattner | 2008-01-06 | 1 | -2/+2 |
| * | remove explicit isStore flags that are now inferrable. | Chris Lattner | 2008-01-06 | 1 | -3/+2 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 | 1 | -2/+1 |
| * | Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materia... | Evan Cheng | 2007-12-12 | 1 | -0/+1 |
| * | Unifacalize the CALLSEQ{START,END} stuff. | Bill Wendling | 2007-11-13 | 1 | -5/+4 |
| * | Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack | Bill Wendling | 2007-11-13 | 1 | -7/+9 |
| * | Add a flag for indirect branch instructions. | Owen Anderson | 2007-11-12 | 1 | -1/+1 |
| * | Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. | Evan Cheng | 2007-09-11 | 1 | -17/+31 |
| * | 80 col. | Evan Cheng | 2007-09-10 | 1 | -4/+6 |
| * | ARM instruction table was modified by adding information to generate multiply... | Raul Herbster | 2007-08-30 | 1 | -42/+57 |
| * | Initial JIT support for ARM by Raul Fernandes Herbster. | Evan Cheng | 2007-08-07 | 1 | -260/+352 |
| * | Indexed loads each has 2 outputs. | Evan Cheng | 2007-08-01 | 1 | -10/+10 |
| * | No more noResults. | Evan Cheng | 2007-07-21 | 1 | -2/+2 |
| * | Change instruction description to split OperandList into OutOperandList and | Evan Cheng | 2007-07-19 | 1 | -187/+211 |
| * | Remove clobbersPred. Add an OptionalDefOperand to instructions which have the... | Evan Cheng | 2007-07-10 | 1 | -112/+98 |
| * | No need for ccop anymore. | Evan Cheng | 2007-07-06 | 1 | -13/+7 |
| * | Do away with ImmutablePredicateOperand. | Evan Cheng | 2007-07-06 | 1 | -1/+1 |
| * | PredicateDefOperand -> OptionalDefOperand. | Evan Cheng | 2007-07-06 | 1 | -3/+3 |
| * | Unbreak the build. | Evan Cheng | 2007-07-05 | 1 | -1/+1 |
| * | Each ARM use predicate operand is now made up of two components. The new comp... | Evan Cheng | 2007-07-05 | 1 | -50/+109 |
| * | Revert the earlier change that removed the M_REMATERIALIZABLE machine | Dan Gohman | 2007-06-26 | 1 | -0/+4 |
| * | Fix the build. | Owen Anderson | 2007-06-22 | 1 | -1/+1 |
| * | Allow predicated immediate ARM to ARM calls. | Evan Cheng | 2007-06-19 | 1 | -0/+7 |
| * | Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad | Dan Gohman | 2007-06-19 | 1 | -4/+0 |
| * | Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. | Evan Cheng | 2007-06-19 | 1 | -0/+6 |
| * | Mark these instructions clobbersPred. They modify the condition code register. | Evan Cheng | 2007-06-06 | 1 | -8/+17 |
