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path: root/lib/Target/ARM/ARMInstrNEON.td
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* Use subclassing to print lane-like immediates (w/o hash) eliminatingAnton Korobeynikov2009-08-081-20/+20
| | | | | | 'no_hash' modifier. Hopefully this will make Daniel happy :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
* Add insert_elt / extract_elt patterns for v4f32 stuff.Anton Korobeynikov2009-08-081-19/+30
| | | | | | Did anyone tests v4f32 ever? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8
* Lane number should be printed w/o hashAnton Korobeynikov2009-08-081-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8
* Use VLDM / VSTM to spill/reload 128-bit Neon registersAnton Korobeynikov2009-08-081-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,Bob Wilson2009-08-081-16/+37
| | | | | | | so I generalized the class for VTRN in the .td file to handle all 3 of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement Neon VTRN instructions. For now, anyway, these are selectedBob Wilson2009-08-081-0/+21
| | | | | | | | | directly from the intrinsics produced by the frontend. If it is more convenient to have a custom DAG node for using these to implement shuffles, we can add that later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak the stuffAnton Korobeynikov2009-08-071-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78425 91177308-0d34-0410-b5e6-96231b3b80d8
* 2 more vdup.32 casesAnton Korobeynikov2009-08-071-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix support to use NEON for single precision fp math.Evan Cheng2009-08-071-41/+83
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement Neon VST[234] operations.Bob Wilson2009-08-061-24/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
* Add parameter to pattern classes to enable an itinerary to be specified for ↵David Goodwin2009-08-061-68/+107
| | | | | | instructions. For now just use the existing itineraries or NoItinerary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
* Neon does not actually have VLD{234}.64 instructions.Bob Wilson2009-08-061-3/+0
| | | | | | | These operations will have to be synthesized from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
* When using NEON for single-precision FP, the NEON result must be placed in ↵David Goodwin2009-08-051-14/+20
| | | | | | D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 col violations.Evan Cheng2009-08-051-9/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78175 91177308-0d34-0410-b5e6-96231b3b80d8
* Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.Bob Wilson2009-08-051-7/+43
| | | | | | | | | | Get rid of yesterday's code to fix the register usage during isel. Select the new DAG nodes to machine instructions. The new pre-alloc pass to choose adjacent registers for these results is not done, so the results of this will generally not assemble yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace dregsingle operand modifier with explicit escaped curly brackets.Bob Wilson2009-08-041-2/+2
| | | | | | | | For other VLDn and VSTn operations, we need to list the multiple registers explicitly anyway, so there's no point in special-casing this one usage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
* Add NEON single-precision FP support for fabs and fneg.David Goodwin2009-08-041-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
* Match common pattern for FNMAC. Add NEON SP support.David Goodwin2009-08-041-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ↵David Goodwin2009-08-041-0/+28
| | | | | | to enable. Added patterns for some binary FP operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate theBob Wilson2009-08-041-0/+8
| | | | | | | results to fixed registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78025 91177308-0d34-0410-b5e6-96231b3b80d8
* Change Neon VLDn intrinsics to return multiple values instead of reallyBob Wilson2009-07-291-26/+26
| | | | | | | | wide vectors. Likewise, change VSTn intrinsics to take separate arguments for each vector in a multi-vector struct. Adjust tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ARM Neon VREV instructions.Bob Wilson2009-07-261-0/+72
| | | | | | | Patch by Anton Korzh, with some modifications from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add some NEON ld / st instruction static encoding.Evan Cheng2009-07-081-4/+24
| | | | | | | | - Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy. Patch by Sean Callanan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75065 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement NEON vst1 instruction.Bob Wilson2009-07-081-0/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75037 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement NEON vld1 instructions.Bob Wilson2009-07-081-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ARM's Advanced SIMD (NEON) instruction set.Bob Wilson2009-06-221-0/+1665
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
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