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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-18/+197
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-10/+10
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-3/+25
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-20/+145
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-502/+824
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-36/+109
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* ARM: add a couple more NEON predicates.Tim Northover2013-10-241-4/+4
| | | | | | | | The fused multiply instructions were added in VFPv4 but are still NEON instructions, in particular they shouldn't be available on a Cortex-M4 not matter how floaty it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193342 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: mark various aliases with their architecture requirements.Tim Northover2013-10-241-4/+4
| | | | | | | | | | If an alias inherits directly from InstAlias then it doesn't get any default "Requires" values, so llvm-mc will allow it even on architectures that don't support the underlying instruction. This tidies up the obvious VFP and NEON cases I found. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-191-9/+102
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+11
| | | | | | | | | This reverts commit r189648. Fixes for the previously failing clang-side arm_neon_intrinsics test cases will be checked in separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189841 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "ARM: Improve pattern for isel mul of vector by scalar."Michael Gottesman2013-08-301-11/+0
| | | | | | | | This reverts commit r189619. The commit was breaking the arm_neon_intrinsic test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189648 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Improve pattern for isel mul of vector by scalar.Jim Grosbach2013-08-291-0/+11
| | | | | | | | | | | In addition to recognizing when the multiply's second argument is coming from an explicit VDUPLANE, also look for a plain scalar f32 reference and reference it via the corresponding vector lane. rdar://14870054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189619 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.Tim Northover2013-08-281-8/+6
| | | | | | | Clang is now generating cleaner IR, so this removes the old variants which should be completely unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189481 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add patterns for vqdmlal with separate vqdmull and vqaddsTim Northover2013-08-281-0/+38
| | | | | | | | | The vqdmlal and vqdmlls instructions are really just a fused pair consisting of a vqdmull.sN and a vqadd.sN. This adds patterns to LLVM so that we can switch Clang's CodeGen over to generating these instead of the special vqdmlal intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189480 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add some negative tests for the recent VFP/NEON instructions.Joey Gouly2013-08-271-2/+2
| | | | | | | Fix two issues I found while writing these tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add natural patterns for vaddhl and vsubhl.Tim Northover2013-08-271-0/+14
| | | | | | | | These instructions aren't particularly complicated and it's well worth having patterns for some reasonably useful LLVM IR that will match them. Soon we should be able to switch Clang over to producing this natural version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189335 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM vcvt encoding when the number of fractional bits is zero.Mihai Popa2013-08-221-0/+19
| | | | | | | | | | | | | The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: remove now unneeded custom Asm convertersTim Northover2013-07-221-28/+0
| | | | | | | | After Ulrich's r180677 (thanks!) TableGen is intelligent enough to handle tied constraints involving complex operands properly, so virtually all of the ARM custom converters are now unnecessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186810 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.Joey Gouly2013-07-191-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186688 91177308-0d34-0410-b5e6-96231b3b80d8
* Change 'n' to 'N' to keep consistent with other instructions.Joey Gouly2013-07-181-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186576 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add NEON instructions VCVT{A, N, P, M}.Joey Gouly2013-07-181-0/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the extra leading 0 from VMAXNMND.Joey Gouly2013-07-181-1/+1
| | | | | | | | | The N3VDIntnp pattern takes bits<5> and I gave it 6 bits. Thanks to Jiangning Liu for spotting it! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186568 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add support for the NEON instructions vmaxnm/vminnm.Joey Gouly2013-07-171-0/+45
| | | | | | | | This adds a new class for non-predicable NEON instructions and a new DecoderNamespace for v8 NEON instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186504 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add optional datatype suffix to NEON mvn asm syntax.Jim Grosbach2013-06-181-1/+6
| | | | | | rdar://14194152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Enforce decoding rules for VLDn instructionsAmaury de la Vieuville2013-06-111-40/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix VEXT encoding corner caseTim Northover2013-05-311-5/+6
| | | | | | | | | | The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
* VSTn instructions have a number of encoding constraints which are not ↵Mihai Popa2013-05-201-21/+21
| | | | | | implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/NEON: Pattern match vector integer abs to vabs.Benjamin Kramer2013-04-261-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180604 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add VACLT and VACLE assembly aliases.Jim Grosbach2013-04-151-0/+18
| | | | | | | | | These are aliases for VACGT and VACGE, respectively, with the source operands reversed. rdar://13638090 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON: Don't need COPY_TO_REGCLASS in patternArnold Schwaighofer2013-02-191-3/+1
| | | | | | | | | | | | | | | | | In my previous commit: "Merge a f32 bitcast of a v2i32 extractelt A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers." I added a pattern containing a copy_to_regclass. The copy_to_regclass is actually not needed. radar://13191881 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175555 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON: Merge a f32 bitcast of a v2i32 extracteltArnold Schwaighofer2013-02-191-0/+6
| | | | | | | | | | | | | | A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175520 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-141-0/+5
| | | | | | | | | | | | | | | assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Adding support for llvm.arm.neon.vaddl[su].* and"Bob Wilson2012-12-201-40/+4
| | | | | | | This reverts r170694. The operations can be represented in IR without adding any new intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170765 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding support for llvm.arm.neon.vaddl[su].* andRenato Golin2012-12-201-4/+40
| | | | | | | | | | llvm.arm.neon.vsub[su].* intrinsics. Patch by Pete Couperus <pjcoup@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170694 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure FABS on v2f32 and v4f32 is legal on ARM NEONAnton Korobeynikov2012-11-161-6/+9
| | | | | | | This fixes PR14359 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."Jakob Stoklund Olesen2012-10-261-15/+17
| | | | | | | Keep the integer_insertelement test case, the new coalescer can handle this kind of lane insertion without help from pseudo-instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166835 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: v1i64 and v2i64 VBSL intrinsic support.Jim Grosbach2012-10-151-0/+17
| | | | | | rdar://12502028 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165981 91177308-0d34-0410-b5e6-96231b3b80d8
* Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng2012-10-101-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165673 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LLVM support for Swift.Bob Wilson2012-09-291-4/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach2012-09-211-2/+29
| | | | | | | | | | | The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164340 91177308-0d34-0410-b5e6-96231b3b80d8
* Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng2012-09-181-0/+33
| | | | | | | | | | aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164089 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-2/+2
| | | | | | Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate ↵James Molloy2012-09-061-17/+15
| | | | | | to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163298 91177308-0d34-0410-b5e6-96231b3b80d8
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-151-0/+34
| | | | | | unaligned access. rdar://12091029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct loads for vector types during extending-load operations.Tim Northover2012-08-131-36/+36
| | | | | | | | | Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161748 91177308-0d34-0410-b5e6-96231b3b80d8
* More replacing of target-dependent intrinsics with target-indepdent Joel Jones2012-07-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8
* This is one of the first steps at moving to replace target-dependent Joel Jones2012-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | intrinsics with target-indepdent intrinsics. The first instruction(s) to be handled are the vector versions of count leading zeros (ctlz). The changes here are to clang so that it generates a target independent vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector ctlzs with target-independent ctlzs. There are also changes to an existing test case in llvm for ARM vector count instructions and a new test for the bitcode upgrade. <rdar://problem/11831778> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160200 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Allow more flexible patterns in NEON formats.Jim Grosbach2012-07-101-53/+53
| | | | | | | | | Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames2012-04-271-4/+4
| | | | | | | | <rdar://problem/11325085>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8
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