| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Remove comments which don't add much to .s readibility. | Evan Cheng | 2009-09-09 | 1 | -5/+5 |
| * | Calls clobber FPSCR. | David Goodwin | 2009-09-03 | 1 | -2/+2 |
| * | Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed. | Evan Cheng | 2009-08-31 | 1 | -4/+3 |
| * | Print a nl before pic labels so they start at a new line. This makes assembly... | Evan Cheng | 2009-08-28 | 1 | -1/+1 |
| * | v4, v5 does not support sxtb / sxth. | Evan Cheng | 2009-08-28 | 1 | -3/+9 |
| * | Rename ARM "lane_cst" operands to "nohash_imm" since they are used for | Bob Wilson | 2009-08-21 | 1 | -1/+1 |
| * | Fix an obvious copy-n-paste bug. | Evan Cheng | 2009-08-20 | 1 | -1/+1 |
| * | Update Cortex-A8 instruction itineraries for integer instructions. | David Goodwin | 2009-08-19 | 1 | -72/+72 |
| * | Fix revsh pattern. | Evan Cheng | 2009-08-18 | 1 | -1/+1 |
| * | Also shrink immediate branches; also more assembler workarounds. | Evan Cheng | 2009-08-14 | 1 | -4/+5 |
| * | Shrink ADR and LDR from constantpool late during constantpool island pass. | Evan Cheng | 2009-08-14 | 1 | -4/+5 |
| * | Finalize itineraries for cortex-a8 integer multiply | David Goodwin | 2009-08-13 | 1 | -1/+1 |
| * | Enhance the InstrStage object to enable the specification of an Itinerary wit... | David Goodwin | 2009-08-12 | 1 | -1/+1 |
| * | Shrink Thumb2 movcc instructions. | Evan Cheng | 2009-08-12 | 1 | -2/+9 |
| * | 80 col violation. | Evan Cheng | 2009-08-12 | 1 | -5/+5 |
| * | Shrinkify Thumb2 r = add sp, imm. | Evan Cheng | 2009-08-11 | 1 | -3/+3 |
| * | Shrinkify Thumb2 load / store multiple instructions. | Evan Cheng | 2009-08-11 | 1 | -10/+20 |
| * | Split EVT into MVT and EVT, the former representing _just_ a primitive type, ... | Owen Anderson | 2009-08-11 | 1 | -4/+4 |
| * | Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ... | Owen Anderson | 2009-08-10 | 1 | -4/+4 |
| * | Add support to reduce most of 32-bit Thumb2 arithmetic instructions. | Evan Cheng | 2009-08-10 | 1 | -4/+3 |
| * | Use subclassing to print lane-like immediates (w/o hash) eliminating | Anton Korobeynikov | 2009-08-08 | 1 | -2/+2 |
| * | tADDhirr should target GPR, not tGPR. | Evan Cheng | 2009-08-08 | 1 | -1/+1 |
| * | tBfar is bl, which clobbers LR. | Evan Cheng | 2009-08-07 | 1 | -0/+1 |
| * | It turns out most of the thumb2 instructions are not allowed to touch SP. The... | Evan Cheng | 2009-08-07 | 1 | -7/+23 |
| * | Add parameter to pattern classes to enable an itinerary to be specified for i... | David Goodwin | 2009-08-06 | 1 | -88/+89 |
| * | Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. | Evan Cheng | 2009-08-04 | 1 | -3/+4 |
| * | Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same | Evan Cheng | 2009-08-01 | 1 | -28/+32 |
| * | Make sure Thumb2 uses the right call instructions. | Evan Cheng | 2009-07-29 | 1 | -7/+53 |
| * | - Fix an obvious copy and paste error. | Evan Cheng | 2009-07-29 | 1 | -1/+1 |
| * | In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is un... | Evan Cheng | 2009-07-28 | 1 | -1/+1 |
| * | Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isT... | David Goodwin | 2009-07-27 | 1 | -17/+17 |
| * | Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a ... | Evan Cheng | 2009-07-26 | 1 | -3/+3 |
| * | Since we have moved unified assembly, switch to ADR instruction instead of a ... | Evan Cheng | 2009-07-23 | 1 | -16/+5 |
| * | Use getTargetConstant instead of getConstant since it's meant as an constant ... | Evan Cheng | 2009-07-22 | 1 | -6/+7 |
| * | Don't forget D16 - D31 are clobbered by calls and sjlj eh. | Evan Cheng | 2009-07-22 | 1 | -2/+4 |
| * | Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-cau... | Evan Cheng | 2009-07-22 | 1 | -2/+2 |
| * | Do not select tSXTB / tSXTH in thumb2 mode. | Evan Cheng | 2009-07-21 | 1 | -4/+4 |
| * | Fix tSUBspi operand definition. It reads and writes sp, which is a high regis... | Evan Cheng | 2009-07-17 | 1 | -1/+1 |
| * | 1. In Thumb mode, select tBx instead of ARM variants. | Evan Cheng | 2009-07-14 | 1 | -2/+2 |
| * | Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is f... | Evan Cheng | 2009-07-11 | 1 | -0/+10 |
| * | Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies... | Evan Cheng | 2009-07-11 | 1 | -189/+186 |
| * | We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. Th... | Evan Cheng | 2009-07-10 | 1 | -36/+28 |
| * | Add a thumb2 pass to insert IT blocks. | Evan Cheng | 2009-07-10 | 1 | -9/+0 |
| * | Added Thumb IT instruction. | Evan Cheng | 2009-07-09 | 1 | -0/+9 |
| * | Use common code for both ARM and Thumb-2 instruction and register info. | David Goodwin | 2009-07-08 | 1 | -10/+10 |
| * | Checkpoint Thumb2 Instr info work. Generalized base code so that it can be sh... | David Goodwin | 2009-07-08 | 1 | -11/+11 |
| * | Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. | David Goodwin | 2009-06-30 | 1 | -8/+9 |
| * | A few more load instructions. | Evan Cheng | 2009-06-30 | 1 | -5/+5 |
| * | Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only ... | David Goodwin | 2009-06-29 | 1 | -10/+10 |
| * | Implement Thumb2 ldr. | Evan Cheng | 2009-06-29 | 1 | -14/+14 |
